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參數(shù)資料
| 型號(hào)： | K1B6416B6C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory |
| 中文描述： | 4Mx16位同步突發(fā)統(tǒng)一晶體管隨機(jī)存取存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 37/46頁(yè) |
| 文件大?。?/td> | 768K |
| 代理商： | K1B6416B6C |
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Revision 1.0
January 2005
K1B6416B6C
- 37 -
U
t
RAM
Fig.31 TIMING WAVEFORM OF BURST READ STOP by CS
[Latency=5,Burst Length=4,WP=Low enable]
(WE=V
IH
, MRS=V
IH
)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADV
Address
CS
LB, UB
Data
OE
CLK
DQ0
Undefined
t
CD
Don’t Care
Valid
Latency 5
Valid
t
ADVS
t
ADVH
t
AS(B)
t
AH(B)
t
CSS(B)
T
t
OH
t
CHZ
SYNCHRONOUS BURST READ STOP TIMING WAVEFORM
WAIT
t
BEL
t
OEL
t
BLZ
t
OLZ
t
CSLH
(SYNCHRONOUS BURST READ STOP TIMING)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBSADV
should be met
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5
μ
s.
t
CSHP
High-Z
0
High-Z
t
WL
t
WH
t
WZ
t
WL
DQ1
t
BSADV
～
Table 35. BURST READ STOP AC CHARACTERISTICS
Symbol
Speed
Units
Symbol
Speed
Units
Min
Max
Min
Max
t
BSADV
t
CSLH
t
CSHP
t
BEL
t
OEL
t
BLZ
t
OLZ
12
7
5
1
1
5
5
-
-
-
-
-
-
-
ns
ns
ns
t
CD
t
OH
t
CHZ
t
WL
t
WH
t
WZ
-
3
-
-
-
-
10
-
12
10
12
12
ns
ns
ns
ns
ns
ns
clock
clock
ns
ns
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