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參數(shù)資料
| 型號： | K1B6416B6C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory |
| 中文描述： | 4Mx16位同步突發(fā)統(tǒng)一晶體管隨機(jī)存取存儲器 |
| 文件頁數(shù)： | 23/46頁 |
| 文件大?。?/td> | 768K |
| 代理商： | K1B6416B6C |
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Revision 1.0
January 2005
K1B6416B6C
- 23 -
U
t
RAM
ASYNCHRONOUS WRITE TIMING WAVEFORM
Table 21. ASYNCHRONOUS WRITE AC CHARACTERISTICS
(WE Controlled)
1. t
WP
(min)=70ns for continuous write operation over 50 times.
Symbol
Speed
Units
Symbol
Speed
Units
Min
Max
Min
Max
t
WC
t
CW
t
AW
t
BW
t
WP
70
60
60
60
-
-
-
-
-
ns
ns
ns
ns
ns
t
AS
t
WR
t
DW
t
DH
0
0
-
-
-
-
-
ns
ns
ns
ns
ns
30
0
10
55
1)
t
CSHP(A)
Address
Data Valid
UB, LB
WE
Data in
t
WC
t
CW
t
BW
t
WP
t
DH
t
DW
t
WR
t
AW
t
AS
CS
Data out
High-Z
High-Z
t
WC
t
AS
t
WR
Data Valid
t
DH
t
DW
t
WHP
t
WP
t
CW
t
AW
t
BW
Fig.17 TIMING WAVEFORM OF WRITE CYCLE(1)
(MRS=V
IH,
OE=V
IH
, WAIT=High-Z, WE Controlled)
(ASYNCHRONOUS WRITE CYCLE - WE Controlled)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high or WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change.
t
WR
is applied in case a write ends with CS or WE going high.
5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored.
6. Condition for continuous write operation over 50 times : t
WP
(min)=70ns
t
CSHP(A)
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