參數(shù)資料
型號(hào)： K1B6416B6C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory
中文描述： 4Mx16位同步突發(fā)統(tǒng)一晶體管隨機(jī)存取存儲(chǔ)器
文件頁(yè)數(shù)： 11/46頁(yè)
文件大小： 768K
代理商： K1B6416B6C
Revision 1.0
January 2005
K1B6416B6C
- 11 -
U
t
RAM
MODE REGISTER SETTING OPERATION
The device has several modes : Asynchronous Page Read mode, Asynchronous Write mode, Synchronous Burst Read mode, Syn-
chronous Burst Write mode, Standby mode and Partial Array Refresh(PAR) mode.
Partial Array Refresh(PAR) mode is defined through Mode Register Set(MRS) option. Mode Register Set(MRS) option also defines
Burst Length, Burst Type, Wait Polarity and Latency Count at Synchronous Burst Read/Write mode.
Mode Register Set (MRS)
The mode register stores the data for controlling the various operation modes of UtRAM. It programs Partial Array Refresh(PAR),
Burst Length, Burst Type, Latency Count and various vendor specific options to make UtRAM useful for a variety of different applica-
tions. The default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes.
The mode register is written by driving CS, ADV, WE, UB, LB
and MRS to V
IL
and driving OE to V
IH
during valid address. The mode
register is divided into various fields depending on the fields of functions. The Partial Array Refresh(PAR) field uses A0~A4, Burst
Length field uses A5~A7, Burst Type uses A8, Latency Count uses A9~A11, Wait Polarity uses A13, Operation Mode uses A14~A15
and Driver Strength uses A16~A17.
Refer to the Table below for detailed Mode Register Setting. A18~A21 addresses are "Don’t care" in Mode Register Setting.
Table 6. Mode Register Setting according to field of function
NOTE : DS(Driver Strength), MS(Mode Select), WP(Wait Polarity), Latency(Latency Count), BT(Burst Type),
BL(Burst Length), PAR(Partial Array Refresh), PARA(Partial Array Refresh Array),
PARS(Partial Array Refresh Size), RFU(Reserved for Future Use)
Table 7. Mode Register Set
NOTE : The address bits other than those listed in the table above are reserved.
For example, Burst Length address bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0.
If the reserved address bits are input, then the mode will be set into the default mode. Each field has its own default mode and
these default modes are written in blue-bold in the table above.
But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up.
A12 is a reserved bit for future use. A12 must be set as "0".
Not all the mode settings are tested.
Per the mode settings to be tested, please contact Samsung Product Planning team.
256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns
.
* The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then imple-
ment at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode.
* The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the
transition from Synchronous burst write operation to Asynchronous write operation is prohibited.
Address
A17~A16
A15~A14
A13
A12
A11~A9
A8
A7~A5
A4~A3
A2
A1~A0
Function
DS
MS
WP
RFU
Latency
BT
BL
PAR
PARA
PARS
Driver Strength
Mode Select
A17
A16
DS
A15
A14
MS*
0
0
Full Drive
0
0
Async. 4 Page Read / Async. Write
0
1
1/2 Drive
0
1
Sync. Burst Read / Async. Write
1
0
1/4 Drive
1
0
Sync. Burst Read / Sync. Burst Write
WAIT Polarity
RFU
Latency Count
Burst Type
Burst Length
A13
WP
A12
RFU
A11
A10
A9
Latency
A8
BT
A7
A6
A5
BL
0
Low Enable
0
Must
0
0
0
3
0
Linear
0
1
0
4 word
1
High Enable
1
-
0
0
1
4
1
Interleave
0
1
1
8 word
0
1
0
5
1
0
0
16 word
0
1
1
6
1
1
1
Full(256 word)
Partial Array Refresh
PAR Array
PAR Size
A4
A3
PAR
A2
PARA
A1
A0
PARS
1
0
PAR Enable
0
Bottom Array
0
0
Full Array
1
1
PAR Disable
1
Top Array
0
1
3/4 Array
1
0
1/2 Array
1
1
1/4 Array
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