參數(shù)資料
型號: K1B6416B6C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory
中文描述: 4Mx16位同步突發(fā)統(tǒng)一晶體管隨機存取存儲器
文件頁數(shù): 15/46頁
文件大?。?/td> 768K
代理商: K1B6416B6C
Revision 1.0
January 2005
K1B6416B6C
- 15 -
U
t
RAM
SYNCHRONOUS BURST OPERATION TERMINOLOGY
WAIT Control(WAIT)
The WAIT signal is the device’s output signal which indicates to the host system when the device’s data-out or data-in is valid.
To be compatible with the Flash interfaces of various microprocessor types, the WAIT polarity(WP) can be configured. The polarity
can be programmed to be either low enable or high enable.
For the timing of WAIT signal, the WAIT signal should be set active one clock prior to the data regardless of Read or Write cycle.
Burst Type
The device supports Linear type burst sequence and Interleave type burst sequence. Linear type burst sequentially increments the
burst address from the starting address. The detailed Linear and Interleave type burst address sequence is shown in burst sequence
table in next page.
1
2
3
4
5
6
7
8
9
10
11
12
13
ADV
Read
Data out
CLK
DQ0
DQ1
0
DQ2
Fig.11 WAIT Control and Read/Write Latency Control(LATENCY : 5, Burst Length : 4, WP : Low Enable)
Write
Data in
D0
D1
D2
DQ3
D3
CS
Latency 5
Latency 5
High-Z
WAIT
High-Z
WAIT
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