參數(shù)資料
型號(hào)： K1B6416B6C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory
中文描述： 4Mx16位同步突發(fā)統(tǒng)一晶體管隨機(jī)存取存儲(chǔ)器
文件頁數(shù)： 35/46頁
文件大小： 768K
代理商： K1B6416B6C
Revision 1.0
January 2005
K1B6416B6C
- 35 -
U
t
RAM
1
2
3
4
5
6
7
8
9
10
11
12
13
ADV
Address
CS
LB, UB
Data in
WE
CLK
D0
D1
D2
D3
Valid
t
ADVS
t
ADVH
t
AS(B)
t
AH(B)
t
CSS(B)
T
t
DHC
Fig.29 TIMING WAVEFORM OF BURST WRITE CYCLE(1)
[Latency=5,Burst Length=4,WP=Low enable]
(OE=V
IH
, MRS=V
IH
)
- CS Toggling Consecutive Burst Write
SYNCHRONOUS BURST WRITE TIMING WAVEFORM
(SYNCHRONOUS BURST WRITE CYCLE - CS Toggling Consecutive Burst Write)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
4. D2 is masked by UB and LB.
5. Burst Cycle Time(tBC) should not be over 2.5
μ
s.
WAIT
0
t
WES
t
WEH
t
DS
t
DHC
Don’t Care
t
BMS
t
BMH
Latency 5
High-Z
t
WL
t
WH
t
BS
t
BH
D0
t
WHP
t
CSHP
t
WZ
t
WL
Latency 5
Valid
t
WH
t
BEADV
t
BC
～
Table 33. BURST WRITE AC CHARACTERISTICS
(CS Toggling Consecutive Burst)
Symbol
Speed
Units
Symbol
Speed
Units
Min
Max
Min
Max
t
CSHP
t
BS
t
BH
t
BMS
t
BMH
t
WES
t
WEH
5
5
5
7
7
5
5
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
t
WHP
t
DS
t
DHC
t
WL
t
WH
t
WZ
5
5
3
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
10
12
12
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