參數(shù)資料
型號(hào)： JTS8388B
英文描述： JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form
中文描述： JTS8388B [更新9 / 03。 47頁] ADC的8位1死GSPS的形式
文件頁數(shù)： 8/47頁
文件大?。?/td> 785K
代理商： JTS8388B
8
JTS8388B
2104A–BDC–09/03
Notes:
1.
The clock inputs may be indifferently entered in differential or single-ended mode, using ECL levels or 4 dBm typical power level into the
50
termination resistor of the in-phase clock input. (4 dBm into 50
clock input correspond to 10 dBm power level for the clock
generator).
Differential output buffers are internally loaded by 75 W resistors. Buffer bias current = 11 mA
Specified loading conditions for digital outputs:
50 or 75 W controlled impedance traces properly 50/75 W terminated, or unterminated 75 W controlled impedance traces.
Controlled impedance traces far-end loaded by 1 standard ECLinPS register from Motorola (e.g.: 10E452) (typical input parasitic capac-
itance of 1.5 pF including package and ESD protections).
See “Definitions of Terms” on page 28.
Histogram testing based on sampling of a 10 MHz sinewave at 50 Msps
Output error amplitude < ±4 LSB around worst code
Maximum jitter value obtained for single-ended clock input
At 1 Gsps, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate.
Termination load parasitic capacitance derating values:
50 or 75 W controlled impedance traces properly 50 /75 W terminated: 60 ps / pF or 75 ps per additional ECLinPS load.
Unterminated (source terminated) 75W controlled impedance lines: 100 ps / pF or 150 ps per additional ECLinPS termination load.
10. Apply proper 50/75 W impedance traces propagation time derating values: 6 ps / mm (155 ps/inch) for TSEV8388B Evaluation Board.
11. Values for TOD and TDR track each other over temperature (1 percent variation for TOD - TDR per 100 degrees Celsius temperature varia-
tion). Therefore, TOD - TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between each
Data TOD and TDR effect can be considered negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps
apart. The same is true for the TOD and TDR maximum values. See “Applying the JTS8388B” on page 30.
2.
3.
4.
5.
6.
7.
8.
9.
Switching Performance and Characteristics
-
See Figures 2 and 3 on page 9
Maximum clock frequency (binary output coding)
Fs
1
1.4
Gsps
Maximum clock frequency (Gray output coding)
Fs
1
1.9
Gsps
Minimum clock frequency
Fs
IV
10
Msps
Minimum clock pulse width (high)
TC1
IV
0.285
0.500
50
ns
Minimum clock pulse width (low)
TC2
IV
0.350
0.500
50
ns
Aperture delay
(4)
TA
IV
100
250
400
ps
Aperture uncertainty
(4)(7)
Jitter
IV
0.4
0.6
ps (rms)
Data output delay
(3)(4)(9)(10)
TOD
Full
IV
1150
1360
1660
ps
Output rise/fall time for data (20% - 80%)
(9)
TR/TF
Full
IV
250
350
550
ps
Output rise/fall time for data ready (20% - 80%)
(9)
TR/TF
Full
IV
250
350
550
ps
Data ready output delay
(4)(8)(9)(10)
TDR
Full
IV
1110
1320
1620
ps
Data ready reset relay
TRDR
720
1000
ps
(11)
TOD-
TDR
40
40
40
ps
See timing diagram at 1 Gsps
TD1
Full
IV
460
460
460
ps
Data pipeline delay
TPD
IV
4
Clock
cycles
Electrical Operating Characteristics (Continued)
V
EE
= D
VEE
= -5 V; V
CC
= 5 V; V
IN
- V
INB
= 500 mVpp full-scale differential input
Digital outputs 75 or 50
differentially terminated; T
J
(typical) = 70
°
C. Full temperature range: -55
°
C < T
J
< 125
°
C
Parameter
Symbol
Temp
Test
Level
Min.
Typ.
Max.
Unit
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