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參數(shù)資料
| 型號(hào)： | JTS8388B |
| 英文描述： | JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form |
| 中文描述： | JTS8388B [更新9 / 03。 47頁(yè)] ADC的8位1死GSPS的形式 |
| 文件頁(yè)數(shù)： | 12/47頁(yè) |
| 文件大?。?/td> | 785K |
| 代理商： | JTS8388B |
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JTS8388B
2104A–BDC–09/03
Chip Description
Table 4.
JTS8388B Chip Functions Description
Symbol
Pad Number
Function
GND
20, 24, 26, 28, 33, 35, 37
Analog ground
Pads n
°
20, 24, 26, 28, 37 are double
Pads n
°
26, 33, 35 are single
14 bonding wires are available for analog ground access
V
PLUSD
1, 11
Digital positive supply (0 V for ECL compatibility, 2.4 V for LVDS
compatibility). 2 double pads
V
CC
19, 21, 23, 30, 39, 40
5 V analog supply
V
EE
22, 29, 31
-5 V analog supply
D
VEE
6
-5 V digital supply
VIN
34
In-phase (+) analog input signal of the differential Sample & Hold
preamplifier
VINB
36
Inverted phase (-) analog input signal
CLK
25
In-phase (+) ECL clock input
CLKB
27
Inverted phase (-) ECL clock input
D0, D1, D2, D3, D4,
D5, D6, D7
16, 14, 12, 9, 4, 2, 45, 43
In-phase (+) digital outputs
D0 is the LSB. D7 is the MSB
D0B, D1B, D2B, D3B,
D4B, D5B, D6B, D7B
17, 15, 13, 10, 5, 3, 46, 44
Inverted phase (-) digital outputs.
D0B is the inverted LSB. D7B is the inverted MSB
OR
41
In-phase (+) out-of-range output
Out-of-range goes high on the leading edge of code 0 or code 256
ORB
42
Inverted phase (-) out-of-range output
DR
7
In-phase (+) output of Data Ready signal
DRB
8
Inverted phase (-) output of Data Ready signal
GORB
18
Gray or binary select output format control pad
Binary output format if GORB is floating or tied at V
CC
Gray output format if GORB is connected to ground (0 V)
GAIN
38
ADC gain adjust pad
DIOD/DRRB
32
DIOD: die junction temperature measurement pad
Can be left floating or grounded if not used
DRRB: asynchronous data ready reset function
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