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參數(shù)資料
| 型號(hào)： | JTS8388B |
| 英文描述： | JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form |
| 中文描述： | JTS8388B [更新9 / 03。 47頁] ADC的8位1死GSPS的形式 |
| 文件頁數(shù)： | 14/47頁 |
| 文件大?。?/td> | 785K |
| 代理商： | JTS8388B |
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14
JTS8388B
2104A–BDC–09/03
Note:
1. Coordinates are relative to pad centers. The coordinates origin (0, 0) is at the center of the die.
All dimensions are given in microns. Pad 1 is one pointed at by the arrow in Figure 4 on page 15
Distance between pad (glass window) and inner edge of seaf-ring: 40 μm.
Die size (inner edge of seal-ring: (-1175, -1455) (1175, 1455).
Die size (including scribe line): (-1230, -1510) (1230, 1510) (2.46 x 3.02 mm
2
).
Actual die size (after separation): (-1220, -1500) (1220, 1500) (2.44 mm x 3.00 mm).
2. GORB tied to V
CC
or floating: binary output data format. GORB tied to GND: gray output data format.
3. The common mode level of the output buffers is 1.2 V below the positive digital supply.
For ECL compatibility the positive digital supply must be set at 0 V (ground).
For LVDS compatibility (output common mode at 1.2 V) the positive digital supply must be set at 2.4 V.
If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive
digital supply level in the same proportion in order to spare power dissipation.
36
1085
-595
V
IN
B
Inverted phase (-) analog input
double pad
37
1085
-345
GND
Analog ground
double pad
38
1085
-145
GAIN
ADC gain adjust input
39
1085
55
V
CC
5 V supply
double pad
40
1085
265
V
CC
5 V supply
41
1085
425
OR
In-phase (+) out-of-range digital output
42
1085
585
ORB
Inverted phase (-) out-of-range digital output
43
1085
745
D7
In-phase (+) digital output, bit 7, most significant bit
44
1085
905
D7B
Inverted phase (-) digital output, bit 7
45
1085
1065
D6
In-phase (+) digital output, bit 6
46
1085
1225
D6B
Inverted phase (-) digital output, bit 6
Table 5.
JTS8388B Chip Pad List, Coordinates and Corresponding Functions (Continued)
Pad
Number
PosX
PosY
Chip Pad Function
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