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參數(shù)資料
| 型號(hào)： | JTS8388B |
| 英文描述： | JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form |
| 中文描述： | JTS8388B [更新9 / 03。 47頁] ADC的8位1死GSPS的形式 |
| 文件頁數(shù)： | 33/47頁 |
| 文件大?。?/td> | 785K |
| 代理商： | JTS8388B |
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33
JTS8388B
2104A–BDC–09/03
Thus, the differential analog input preamplifier will fully reject the local ground noise (and
any capacitively and inductively coupled noise) as common mode effects.
In a typical single-ended configuration, enter on the (VIN) input pad, with the inverted
phase input pad (VINB) grounded through the 50
termination resistor.
In a single-ended input configuration, the in-phase input amplitude is 0.5 V, centered on
0 V (or -2 dBm into 50
).
The inverted phase input is at ground potential through the 50
termination resistor.
Figure 29.
Typical Single Ended Analog Input Configuration
Clock Inputs (CLK)
(CLKB)
The JTS8388B can be clocked at full speed without noticeable performance degradation
in either the differential or single-ended configuration.
This is explained by the fact the ADC uses a differential preamplifier stage for the clock
buffer, which has been designed to be entered either in a differential or single-ended
mode.
Single-ended Clock Input
(Ground Common Mode)
Although the clock inputs were intended to be driven differentially with nominal
-0.8 V/-1.8 V ECL levels, the JTS8388B clock buffer can manage a single-ended sine-
wave clock signal centered around 0 V. This is the most convenient clock input
configuration as it does not require the use of a power splitter.
No performance degradation (e.g. due to timing jitters) is observed in this particular sin-
gle-ended configuration up to 1.2 Gsps Nyquist conditions (Fin = 600 MHz).
This is true so long as the inverted phase clock input pad is 50
terminated very closely
to one of the neighboring shield ground pads, which constitutes the local ground refer-
ence for the in-phase clock input.
Thus, the JTS8388B differential clock input buffer will fully reject the local ground noise
(and any capacitively and inductively coupled noise) as common mode effects.
Moreover, a very low-phase noise sinewave generator must be used for enhanced jitter
performance.
The typical in-phase clock input amplitude is 1 V, centered on a 0 V (ground) common
mode.
This corresponds to a typical clock input power level of 4 dBm into the 50
termination
resistor.
Do not exceed 10 dBm to avoid saturation of the preamplifier input transistors.
The inverted phase clock input is grounded through the 50
termination resistor.
50
(on package)
1 M
3 pF
-250
250
500 mV
t
[mV]
VIN
VIN =
±
250 mV = 500 mV diff
VIN or VINB double pad (pins 54, 55 or 56, 57)
VIN or VINB
50
Reverse Termination
500 mV
Full-scale
Analog Input
VINB = 0 V
VINB
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