參數資料
型號: JTS8388B
英文描述: JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form
中文描述: JTS8388B [更新9 / 03。 47頁] ADC的8位1死GSPS的形式
文件頁數: 34/47頁
文件大小: 785K
代理商: JTS8388B
34
JTS8388B
2104A–BDC–09/03
Figure 30.
Single-ended Clock Input (Ground Common Mode)
VLCLK common mode = 0 V; VCLKB = 0 V; 4 dBm typical clock input power level (into 50
termination resistor
Note:
Do not exceed 10 dBm into the 50
termination resistor for single clock input power level.
Differential ECL Clock
Input
The clock inputs can be driven differentially with nominal -0.8 V/-1.8 V ECL levels.
In this mode, a low-phase noise sinewave generator can be used to drive the clock
inputs, followed by a power splitter (hybrid junction) in order to obtain 180 degrees out-
of-phase sinewave signals. Biasing tees can be used for offsetting the common mode
voltage to ECL levels.
Note:
As the biasing tees propagation times are not matching, a tunable delay line is required
in order to ensure the signals are 180 degrees out-of-phase especially at fast clock rates
in the Gsps range.
Figure 31.
Differential Clock Inputs (ECL Levels)
50
(on package)
1 M
0.4 pF
-0.5 V
0.5 V
t
[V]
VCLK
CLK or CLKB double pad (pins 37, 38 or 39, 40)
CLK or CLKB
50
reverse termination
VCLK = 0 V
VCLK
50
(on package)
1 M
0.4 pF
CLK or CLKB double pad (pins 37, 38 or 39, 40)
CLK or CLKB
-2 V
50
reverse termination
-1.8 V
-0.8 V
[mV]
VCLK
t
VCLKB
Common mode = -1.3 V
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