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參數(shù)資料
| 型號： | JTS8388B |
| 英文描述： | JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form |
| 中文描述： | JTS8388B [更新9 / 03。 47頁] ADC的8位1死GSPS的形式 |
| 文件頁數(shù)： | 31/47頁 |
| 文件大?。?/td> | 785K |
| 代理商： | JTS8388B |
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JTS8388B
2104A–BDC–09/03
The external (on board) skew effect has not been taken into account for the specification
of the minimum and maximum values for TOD-TDR.
Principle of Operation
The analog input is sampled on the rising edge of the external clock input (CLK,CLKB)
after a TA (aperture delay) of typically 250 ps.
The digitized data is available after 4 clock periods latency (pipeline delay (TPD)), on
the clock’s rising edge, after 1160 ps typical propagation delay TOD.
The Data Ready differential output signal frequency (DR, DRB) is half the external clock
frequency, that is it switches at the same rate as the digital outputs.
The Data Ready output signal (DR, DRB) switches on the external clock’s falling edge
after a propagation delay TDR of typically 1120 ps.
A Master Asynchronous Reset input command DRRB (ECL-compatible single-ended
input) is available for initializing the differential Data Ready output signal (DR, DRB).
This feature is mandatory in certain applications using interleaved ADCs or using a
single ADC with demultiplexed outputs. Without Data Ready signal initialization, it is
impossible to store the output digital data in a defined order.
Principle of Data Ready
Signal Control by DRRB
Input Command
Data Ready Output Signal
Reset
The Data Ready signal is reset on the falling edge of the DRRB input command, on the
ECL logical low level (-1.8 V). DRRB may also be tied to V
EE
= -5 V for Data Ready out-
put signal Master Reset. As long as DRRB remains at a logical low level, (or tied to
V
EE
= -5 V), the Data Ready output remains at a logical zero and is independent of the
external free-running encoding clock.
The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 720 ps
typical.
TRDR is measured between the -1.3 V point of the falling edge of the DRRB input com-
mand and the zero crossing point of the differential Data Ready output signal (DR,
DRB).
The Data Ready Reset command may be a pulse of 1 ns minimum time width.
Data Ready Output Signal
Restart
The Data Ready output signal restarts on the DRRB command’s rising edge, ECL logi-
cal high levels (-0.8 V).
DRRB may also be grounded, or may be allowed to float, for a normal free-running Data
Ready output signal.
The Data Ready signal restart sequence depends on the logical level of the external
encoding clock, at a DRRB rising edge instant.
The DRRB rising edge occurs when the external encoding clock input (CLK,CLKB)
is LOW:
The Data Ready output’s first rising edge occurs after half a clock period on the
clock falling edge, after a delay time TDR = 1120 ps already defined above.
The DRRB rising edge occurs when the external encoding clock input (CLK,CLKB)
is HIGH:
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