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參數(shù)資料
| 型號： | JTS8388B |
| 英文描述： | JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form |
| 中文描述： | JTS8388B [更新9 / 03。 47頁] ADC的8位1死GSPS的形式 |
| 文件頁數(shù)： | 29/47頁 |
| 文件大小： | 785K |
| 代理商： | JTS8388B |
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JTS8388B
2104A–BDC–09/03
SINAD
Signal to Noise and
Distortion Ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the
RMS sum of all other spectral components, including the harmonics except DC
SNR
Signal to Noise Ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the
RMS sum of all other spectral components excluding the five first harmonics
TA
Aperture Delay
The delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero crossing
point), and the time at which (V
IN
, V
INB
) is sampled
TC
Encoding Clock
Period
TC1 = minimum clock pulse width (high) TC = TC1 + TC2
TC2 = minimum clock pulse width (low)
TD1
Time Delay from Data
to Data Ready
TD1 is the time difference between Data to Data ready
TD2
Time Delay from Data
Ready to Data
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock
period
TF
Fall Time
Time delay for the output data signals to fall from 80% to 20% of delta between the low level
and high level
THD
Total Harmonic
Distortion
The ratio expressed in dBc of the RMS sum of the first five harmonic components, to the
RMS value of the measured fundamental spectral component
TOD
Digital Data
Output Delay
The delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing
point) to the next point of change in the differential output data (zero crossing) with a
specified load
TPD
Pipeline Delay
The number of clock cycles between the sampling edge of an input data and the associated
output data being made available (not taking in account the TOD). For the JTS8388B the
TPD is 4 clock periods
TR
Rise Time
Time delay for the output data signals to rise from 20% to 80% of delta between the low level
and high level
TRDR
Data Ready Reset
Delay
Delay between the falling edge of the Data Ready output asynchronous Reset signal
(DDRB) and the reset to digital zero transition of the Data Ready output signal (DR)
TS
Settling Time
Time delay to achieve 0.2% accuracy at the converter output when an 80% full-scale step
function is applied to the differential analog input
Definitions of Terms
Table 7.
Definitions of Terms (Continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| JTSX8388B-1V1B | A/D CONVERTER |
| JUCA4532 | Optoelectronic |
| JV1-100V | |
| JV1-12V | |
| JV1-18V | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| JTS8388B-1V1B | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:ADC 8-bit 1 GSPS |
| JTS8388B-1V2B | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:ADC 8-bit 1 GSPS |
| JTS922H-DZD1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RAIL TO RAIL HIGH OUTPUT CURRENT DUAL OPERATIONAL AMPLIFIER |
| JTSIY-10-35P | 制造商:Amphenol Corporation 功能描述:CONN MIL-C-27599 CIRC PIN 13 POS SLDR ST PNL MNT 13TERM - Bulk |
| JTSIY-10-98P | 制造商:Amphenol Corporation 功能描述:CONN MIL-C-27599 CIRC PIN 6 POS SLDR ST PNL MNT 6TERM - Bulk |
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