參數(shù)資料
型號: JTS8388B
英文描述: JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form
中文描述: JTS8388B [更新9 / 03。 47頁] ADC的8位1死GSPS的形式
文件頁數(shù): 37/47頁
文件大?。?/td> 785K
代理商: JTS8388B
37
JTS8388B
2104A–BDC–09/03
Each differential output termination length must be kept identical.
It is recommended to decouple the midpoint of the differential termination with a 10 nF
capacitor to avoid common mode perturbation in case of slight mismatch in the differen-
tial output line lengths.
Too large mismatches (keep < a few mm) in the differential line lengths will lead to
switching currents flowing into the decoupling capacitor, in turn leading to switching
ground noise.
The differential output voltage levels (75 or 50
termination) are not ECL standard volt-
age levels. However, it is possible to drive standard logic ECL circuitry like the ECLinPS
logic line from Motorola
.
At sampling rates exceeding 1 Gsps, it may be difficult to trigger the HP16500 or any
other acquisition system with digital outputs.
It becomes necessary to regenerate digital data and Data Ready by means of external
amplifiers, in order to be able to test the JTS8388B at its optimum performance
conditions.
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