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參數(shù)資料
| 型號(hào)： | JTS8388B |
| 英文描述： | JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form |
| 中文描述： | JTS8388B [更新9 / 03。 47頁] ADC的8位1死GSPS的形式 |
| 文件頁數(shù)： | 36/47頁 |
| 文件大?。?/td> | 785K |
| 代理商： | JTS8388B |
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36
JTS8388B
2104A–BDC–09/03
Noise Immunity
Information
Circuit noise immunity performance begins at the design level.
Efforts have been made on the design to make the device as insensitive as possible to
chip environment perturbations resulting from the circuit itself or induced by external cir-
cuitry (cascade stages isolation, internal damping resistors, clamps, internal (on-chip)
decoupling capacitors).
Furthermore, the fully differential operation from the analog input up to the digital output
provides enhanced noise immunity by common mode noise rejection.
Common mode noise voltage induced on the differential analog and clock inputs will be
canceled out by these balanced differential amplifiers.
Moreover, proper active signals shielding has been provided on the chip to reduce the
amount of coupled noise on the active inputs:
The analog inputs and clock inputs of the TS8388B chip have been surrounded by
ground pads, which must be directly connected to the external ground plane.
Digital Outputs
The JTS8388B differential output buffers are internally 75
loaded. The 75
resistors
are connected to the digital ground pads through a -0.8 V level shift diode (see Figures
34 and 35 on page 38 and Figure 36 on page 39).
The JTS8388B output buffers are designed for driving 75
(default) or 50
properly
terminated impedance lines or coaxial cables.
An 11 mA bias current flowing alternately into one of the 75
resistors when switching,
ensures a 0.825 voltage drop across the resistor (unterminated outputs).
The V
PLUSD
positive supply voltage allows the adjustment of the output common mode
level from -1.2 V (V
PLUSD
= 0 V for ECL output compatibility) to 1.2 V (V
PLUSD
= 2.4 V for
LVDS output compatibility). Therefore, the single-ended output voltages vary approxi-
mately between -0.8 V and -1.625 V (outputs unterminated), around -1.2 V common
mode voltage.
Three possible line driving and back termination scenarios are proposed (assuming
V
PLUSD
= 0 V):
1.
75
impedance transmission lines, 75
differentially terminated (Figure 34):
each output voltage varies between -1 V and -1.42 V (respectively 1.4 V and
1 V), leading to ±0.41 V = 0.825 V in differential, around -1.21 V (respectively
1.21 V) common mode for V
PLUSD
= 0 V (respectively 2.4 V).
2.
50
impedance transmission lines, 50
differentially termination (Figure 35):
each output voltage varies between -1.02 V and -1.35 V (respectively 1.38 V and
1.05 V), leading to ±0.33 V = 660 mV in differential, around -1.18 V (respectively
1.21 V) common mode for V
PLUSD
= 0 V (respectively 2.4 V).
3.
75
impedance open transmission lines (Figure 36): each output voltage varies
between -1.6 V and -0.8 V (respectively 0.8 V and 1.6 V), which are true ECL lev-
els, leading to ±0.8 V = 1.6 V in differential, around -1.2 V (respectively 1.2 V)
common mode for V
PLUSD
= 0 V (respectively 2.4 V).
Therefore, it is possible to drive high input impedance storing registers directly, without
terminating the 75
transmission lines.
In the time domain, this means the incident wave will reflect at the 75
transmission
line output and travel back to the generator (i.e. the 75
data output buffer). As the
buffer output impedance is 75
, no back reflection will occur.
Note:
This is no longer true if a 50
transmission line is used, as the latter is not matching the
buffer 75
output impedance.
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