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參數(shù)資料
| 型號(hào)： | JTS8388B |
| 英文描述： | JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form |
| 中文描述： | JTS8388B [更新9 / 03。 47頁] ADC的8位1死GSPS的形式 |
| 文件頁數(shù)： | 41/47頁 |
| 文件大小： | 785K |
| 代理商： | JTS8388B |
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41
JTS8388B
2104A–BDC–09/03
Figure 39.
Differential Output: Open Loaded
Out-of-range Bit
An out-of-range (OR, ORB) bit is provided that reaches a logical high state when the
input exceeds the positive full-scale or falls below the negative full-scale.
When the analog input exceeds the positive full-scale, the digital outputs remain at a
logical high state with OR, ORB at a logical 1.
When the analog input falls below the negative full-scale, the digital outputs remain at a
logical low state with OR, ORB at a logical 1 again.
Gray or Binary Output
Data Format Select
The JTS8388B internal regeneration latches indecision (for inputs very close to the
latches’ threshold) may produce errors in the logic encoding circuitry and lead to large
amplitude output errors.
This is due to the fact that the latches regenerate the internal analog residues into logi-
cal states with a finite voltage gain value (Av) within a given positive amount of time
(t):
Av= exp(
(t)/
τ
), with
τ
as the positive feedback regeneration time constant.
The JTS8388B has been designed for reducing the probability of occurrence of such
errors to approximately 10
-13
(targeted for the JTS8388B at 1 Gsps).
A standard technique for reducing the amplitude of such errors down to ±1 LSB consists
of setting the digital output data in gray code format.
Though the JTS8388B has been designed to feature a Bit Error Rate of 10
-13
with a
binary output format, it is possible for the user to choose between the binary or gray out-
put data format, in order to reduce the amplitude of such errors when they occur, by
storing gray output codes.
Digital data format selection:
Binary output format if GORB is floating or V
CC
Gray output format if GORB is connected to ground (0 V)
1.6 V
75
75
-
+
11 mA
DVEE
75
75
impedance
Out
OutB
1.6 V/0.8 V
Differential output:
0.8 V = 1.6 V
0.8 V/1.6 V
Common mode level: -1.2 V
(-1.2 V below VPLUSD level)
VPLUSD = 2.4 V
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