
13
JTS8388B
2104A–BDC–09/03
J
Table 5.
JTS8388B Chip Pad List, Coordinates and Corresponding Functions
Pad
Number
PosX
PosY
Chip Pad Function
1
880
1365
V
PLUSD
Positive digital supply
double pad
(3)
2
670
1365
D5
In-phase (+) digital output, bit 5 (D7 is the MSB: Bit 7, D0 is the LSB: Bit 0)
3
510
1365
D5B
Inverted phase (-) digital output, bit 5
4
350
1365
D4
In-phase (+) digital output, bit 4
5
190
1365
D4B
Inverted phase (-) digital output, bit 4
6
-20
1365
D
VEE
-5 V digital supply
double pad
7
-230
1365
DR
In-phase (+) data ready
8
-390
1365
DRB
Inverted Phase (-) data ready
9
-550
1365
D3
In-phase (+) digital output, bit 3
10
-710
1365
D3B
Inverted phase (-) digital output, bit 3
11
-920
1365
V
PLUSD
Positive digital supply
double pad
(3)
12
-1085
1115
D2
In-phase (+) digital output, bit 2
13
-1085
955
D2B
Inverted phase (-) digital output, bit 2
14
-1085
795
D1
In-phase (+) digital output, bit 1
15
-1085
635
D1B
Inverted phase (-) digital output, bit 1
16
-1085
475
D0
In-phase (+) digital output, bit 0, least significant bit
17
-1085
315
D0B
Inverted phase (-) digital output, bit 0, least significant bit
18
-1085
155
GORB
Gray or binary data output format select
(2)
19
-1085
-55
V
CC
5 V supply
double pad
20
-1085
-325
GND
Analog ground
double pad
21
-1085
-595
V
CC
5 V supply
double pad
22
-1085
-865
V
EE
-5 V analog supply
double pad
23
-1085
-1135
V
CC
5 V supply
double pad
24
-905
-1365
GND
Analog ground
double pad
25
-655
-1365
CLK
In-phase (+) clock input
double pad
26
-455
-1365
GND
Analog ground
27
-255
-1365
CLKB
Inverted phase (-) clock input
double pad
28
-5
-1365
GND
Analog ground
double pad
29
245
-1365
V
EE
-5 V analog supply
double pad
30
495
-1365
V
CC
5 V supply
double pad
31
745
-1365
V
EE
-5 V analog supply
double pad
32
945
-1365
DIOD/DRRB
Diode input for T
J
monitoring / input for asynchronous data ready reset
33
1085
-1195
GND
Analog ground
34
1085
-995
V
IN
In-phase (+) analog input
double pad
35
1085
-795
GND
Analog ground