參數(shù)資料
型號(hào)： JTS8388B
英文描述： JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form
中文描述： JTS8388B [更新9 / 03。 47頁(yè)] ADC的8位1死GSPS的形式
文件頁(yè)數(shù)： 32/47頁(yè)
文件大?。?/td> 785K
代理商： JTS8388B
32
JTS8388B
2104A–BDC–09/03
The Data Ready output’s first rising edge occurs after one clock period on the clock
falling edge, and a delay TDR = 1120 ps.
Consequently, as the analog input is sampled on the clock’s rising edge, the first digi-
tized data corresponding to the first acquisition (N) after a Data Ready signal restart
(rising edge) is always strobed by the third rising edge of the Data Ready signal.
The time delay (TD1) is specified between the last point of a change in the differential
output data (zero crossing point) to the rising or falling edge of the differential Data
Ready signal (DR, DRB) (zero crossing point).
For normal initialization of the Data Ready output signal, the external encoding clock
signal frequency and level must be controlled. The minimum encoding clock
sampling rate for the ADC is 10 Msps and consequently the clock cannot be
stopped.
One single pad is used for both the DRRB input command and die junction
temperature monitoring. The pad denomination will be DRRB/DIOD (on the former
version the denomination was DIOD).
Temperature monitoring and Data Ready control by DRRB is not possible
simultaneously.
Analog Inputs (VIN)
(VINB)
The analog input full-scale range is 0.5 V (Vpp), or -2 dBm into the 50
termination
resistor.
In the differential mode input configuration, that means 0.25 V on each input, or
±125 mV around 0 V. The input common mode is ground.
The typical input capacitance is 0.4 pF in die form (JTS8388B), not taking into account
the bond wires capacitance.
The input capacitance is mainly due to the pad capacitance, as the ESD protections are
not connected (but present) on the inputs.
Figure 28.
Differential Inputs Voltage Span
Differential Versus Single-
ended Analog Input Operation
The JTS8388B can operate at full speed without any performance degradation in either
a differential or single-ended configuration.
This is explained by the fact that the ADC uses a high-input impedance differential
preamplifier stage, (preceding the Sample and Hold stage), which has been designed in
order to be entered either in differential or single-ended mode.
This is true so long as the out-of-phase analog input pad VINB is 50
terminated very
closely to one of the neighboring shield ground pads (33, 35, 37), which constitute the
local ground reference for the in-phase analog input pad (VIN).
-125
125
[mV]
-250 mV
VIN
(VIN, VINB) =
±
250 mV = 500 mV diff
500 mV
Full-scale
Analog Input
t
VINB
0 V
250 mV
相關(guān)PDF資料
PDF描述
JTSX8388B-1V1B A/D CONVERTER
JUCA4532 Optoelectronic
JV1-100V
JV1-12V
JV1-18V
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
JTS8388B-1V1B 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:ADC 8-bit 1 GSPS
JTS8388B-1V2B 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:ADC 8-bit 1 GSPS
JTS922H-DZD1 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:RAIL TO RAIL HIGH OUTPUT CURRENT DUAL OPERATIONAL AMPLIFIER
JTSIY-10-35P 制造商:Amphenol Corporation 功能描述:CONN MIL-C-27599 CIRC PIN 13 POS SLDR ST PNL MNT 13TERM - Bulk
JTSIY-10-98P 制造商:Amphenol Corporation 功能描述:CONN MIL-C-27599 CIRC PIN 6 POS SLDR ST PNL MNT 6TERM - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*