參數資料
型號: JTS8388B
英文描述: JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form
中文描述: JTS8388B [更新9 / 03。 47頁] ADC的8位1死GSPS的形式
文件頁數: 4/47頁
文件大小: 785K
代理商: JTS8388B
4
JTS8388B
2104A–BDC–09/03
Differential analog input voltage
(full-scale)
V
IN,
V
INB
V
IN
- V
INB
50
differential or
single-ended
±
113
450
±
125
500
±137
550
mV
mVpp
Clock input power level
PCLK PCLKB
50
single-ended clock
input
3
4
10
dBm
Operating temperature range
T
J
Civil: “C” grade
Industrial: “V” grade
Military: “M” grade
0 to 90
-40 to 105
-55 to 125
°
C
Electrical Operating Characteristics
V
EE
= D
VEE
= -5 V; V
CC
= 5 V; V
IN
- V
INB
= 500 mVpp full-scale differential input
Digital outputs 75 or 50
differentially terminated; T
J
(typical) = 70
°
C. Full temperature range: -55
°
C < T
J
< 125
°
C
Parameter
Symbol
Temp
Test
Level
Min.
Typ.
Max.
Unit
Resolution
8
bits
Analog Inputs
Full-scale input voltage range (differential mode)
(0 V common mode voltage)
V
IN
V
INB
Full
IV
-125
-125
125
125
mV
mV
Full-scale input voltage range (single-ended input option)
V
IN
V
INB
Full
IV
-250
0
250
mV
mV
Analog input capacitance (die)
C
IN
IV
0.4
pF
Input bias current
I
IN
IV
10
μA
Input resistance
R
IN
IV
1
M
Full power input bandwidth
FPBW
IV
1.8
GHz
Small signal input bandwidth (10% full-scale)
SSBW
IV
2
GHz
Clock Inputs
Logic compatibility for clock inputs
(1)
ECL or specified clock input
power level in dBm
ECL clock inputs voltages (V
CLK
or V
CLKB
)
Logic 0 voltage
Logic 1 voltage
Logic 0 current
Logic 1 current
V
IL
V
IH
I
IL
I
IH
Full
Full
Full
Full
-1.1
5
5
-1.5
V
V
μA
μA
Clock input power level into 50
termination
dBm into 50
Clock input power level
3
4
10
dBm
Clock input capacitance (die)
C
CLK
0.4
pF
Recommended Conditions of Use (Continued)
Parameter
Symbol
Comments
Min.
Typ.
Max.
Unit
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