參數(shù)資料
型號: JTS8388B
英文描述: JTS8388B [Updated 9/03. 47 Pages] ADC 8-bit 1 Gsps in die form
中文描述: JTS8388B [更新9 / 03。 47頁] ADC的8位1死GSPS的形式
文件頁數(shù): 2/47頁
文件大?。?/td> 785K
代理商: JTS8388B
2
JTS8388B
2104A–BDC–09/03
Simplified Block
Diagram
Figure 1.
Simplified Block Diagram
Functional
Description
The JTS8388B is an 8-bit 1 Gsps ADC based on an advanced high-speed bipolar tech-
nology featuring a cutoff frequency of 25 GHz.
The JTS8388B includes a front-end master/slave Track and Hold stage (Sample and
Hold), followed by an analog encoding stage and interpolation circuitry.
Successive banks of latches regenerate the analog residues into logical data before
entering an error correction circuitry and a resynchronisation stage followed by 75
differential output buffers.
The JTS8388B works in a fully differential mode from analog inputs up to digital outputs.
The JTS8388B features a full power input bandwidth of 2 GHz.
The control pad GORB is provided to select either the gray or binary data output format.
The gain control pad is provided in order to adjust the ADC gain.
The JTS8388B uses only vertical isolated NPN transistors together with oxide-isolated
polysilicon resistors, providing enhanced radiation tolerance (more than 100 kRad total
dose expected radiation).
G=2
T/H
G=1
T/H
G=1
Clock
Buffer
Resistor
Chain
Analog
Encoding
Block
Interpolation
Stages
Regeneration
Latches
Error Correction &
Decode Logic
Output Latches &
Buffers
4
4
5
4
5
8
8
VIN, VINB
CLK
CLKB
GAIN
DRRB DR, DRB
GORB
DATA, DATAB
OR, ORB
Master/Slave Track & Hold
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