參數(shù)資料
型號: HYB18L256160B
廠商: QIMONDA
英文描述: DRAMs for Mobile Applications 256-Mbit Mobile-RAM
中文描述: DRAM的針對移動應(yīng)用256兆移動RAM
文件頁數(shù): 50/58頁
文件大?。?/td> 1766K
代理商: HYB18L256160B
Data Sheet
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
50
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
FIGURE 47
Measurement Conditions for
t
AC
and
t
OH
DQM write mask latency
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
Refresh period (8192 rows)
Self refresh exit time
1) 0
°
C
T
C
70
°
C (comm.); -25
°
C
T
C
85
°
C (ext.);
V
DD
=
V
DDQ
= 1.65V to 1.95V;
2) All parameters assumes proper device initialization.
3) AC timing tests measured at 0.9 V.
4) The transition time
t
T
is measured between
V
IH
and
V
IL
; all AC characteristics assume
t
T
= 1 ns.
5) Specified
t
AC
and
t
OH
parameters are measured with a 30 pF capacity load only as shown in
Figure 47
.
6) If
t
T
(CLK) > 1 ns, a value of (
t
T
/2 - 0.5) ns has to be added to this parameter.
7) If
t
T
> 1 ns, a value of (
t
T
- 1) ns has to be added to this parameter.
8) These parameter account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
9) The write recovery time of
t
= 14 ns allows the use of one clock cycle for the write recovery time when
f
72 MHz. With
f
> 72 MHz
two clock cycles for
t
WR
are mandatory. Qimonda Technologies recommends to use two clock cycles for the write recovery time in all
applications.
t
DQW
t
RC
t
RCD
t
RRD
t
RAS
t
WR
t
RP
t
REF
t
SREX
0
67
19
15
45
14
19
1
100k
64
t
CK
ns
ns
ns
ns
ns
ns
ms
t
CK
8)
8)
8)
8)
9)
8)
Parameter
Symbol
- 7.5
Unit
Note
1)2)3)4)
min.
max.
30 pF
I/O
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