參數(shù)資料
型號(hào): HYB18L256160B
廠商: QIMONDA
英文描述: DRAMs for Mobile Applications 256-Mbit Mobile-RAM
中文描述: DRAM的針對(duì)移動(dòng)應(yīng)用256兆移動(dòng)RAM
文件頁數(shù): 18/58頁
文件大小: 1766K
代理商: HYB18L256160B
Data Sheet
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
18
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
2.4.4
ACTIVE
Before any READ or WRITE commands can be issued to a
bank within the Mobile-RAM, a row in that bank must be
“opened” (activated). This is accomplished via the ACTIVE
command and addresses A0 - A12, BA0 and BA1 (see
Figure 9
), which decode and select both the bank and the
row to be activated. After opening a row (issuing an ACTIVE
command), a READ or WRITE command may be issued to
that row, subject to the
t
RCD
specification. A subsequent
ACTIVE command to a different row in the same bank can
only be issued after the previous active row has been “closed”
(precharged).
The minimum time interval between successive ACTIVE
commands to the same bank is defined by
t
RC
. A subsequent
ACTIVE command to another bank can be issued while the
first bank is being accessed, which results in a reduction of
total row-access overhead. The minimum time interval
between successive ACTIVE commands to different banks is
defined by
t
RRD
.
FIGURE 9
ACTIVE command
FIGURE 10
Bank Activate Timings
TABLE 11
Timing Parameters for ACTIVE Command
'RQW &DUH
%$ %DQN $G GUHVV
5$ 5RZ $G GUHVV
%$ %$
%$
$ $
5$
:(
&$6
5$6
&6
&.(
+LJK
&/.
Parameter
Symbol
- 7.5
Units
Note
min.
max.
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
t
RC
t
RCD
t
RRD
67
19
15
ns
ns
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
1)
1)
W
55'
W
5&'
'RQW &DUH
&/.
5' :5
123
123
123
$& 7
123
$& 7
&RPPDQG
52:
52:
&2/
$ $
%$ [
%$ \
%$ \
%$
%$
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