
Data Sheet
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
38
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
TABLE 14
Timing Parameters for PRECHARGE
2.4.8.2
CONCURRENT AUTO PRECHARGE
A READ or WRITE burst with Auto Precharge enabled can be interrupted by a subsequent READ or WRITE command issued
to a different bank.
Figure 37
shows a READ with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge) to bank m.
The READ to bank m will interrupt the READ to bank n, CAS latency later. The precharge to bank n will begin when the READ
to bank m is registered.
Figure 38
shows a READ with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge) to bank m.
The precharge to bank n will begin when the WRITE to bank m is registered. DQM should be pulled HIGH two clock cycles
prior to the WRITE to prevent bus contention.
Figure 39
shows a WRITE with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge) to bank m.
The precharge to bank n will begin
t
WR
after the new command to bank m is registered. The last valid data-in to bank n is one
clock cycle prior to the READ to bank m.
Figure 40
shows a WRITE with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge) to bank
m. The precharge to bank n will begin
t
WR
after the WRITE to bank m is registered. The last valid data-in to bank n is one clock
cycle prior to the WRITE to bank m.
FIGURE 37
READ with Auto Precharge Interrupted by READ
Parameter
Symbol
- 7.5
Units
Note
min.
max.
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
t
RAS
t
WR
t
RP
45
14
19
100k
—
—
ns
ns
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
1)
1)
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