參數(shù)資料
型號: HB52R168DB
廠商: Hitachi,Ltd.
英文描述: 128 MB Unbuffered SDRAM S.O.DIMM(128 MB 未緩沖同步DRAM S.O.DIMM)
中文描述: 128 MB的無緩沖內(nèi)存的SODIMM(128 MB的未緩沖同步內(nèi)存的SODIMM)
文件頁數(shù): 19/57頁
文件大?。?/td> 860K
代理商: HB52R168DB
HB52R168DB-F
19
Self refresh entry [SELF]:
When this command is input during the IDLE state, the SDRAM module starts
self refresh operation. After the execution of this command, self refresh continues while CKE0 is Low. Since
self refresh is performed internally and automatically, external refresh operations are unnecessary.
Power down mode entry:
When this command is executed during the IDLE state, the SDRAM module
enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial
input circuit.
Self refresh exit:
When this command is executed during self refresh mode, the SDRAM module can exit
from self refresh mode. After exiting from self refresh mode, the SDRAM module enters the IDLE state.
Power down exit:
When this command is executed at the power down mode, the SDRAM module can exit
from power down mode. After exiting from power down mode, the SDRAM module enters the IDLE state.
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of
the SDRAM module. The following table assumes that CKE is high.
Current state
S
RE
CE
W
Address
Command
Operation
Precharge
H
×
×
×
×
×
×
DESL
Enter IDLE after t
RP
Enter IDLE after t
RP
NOP
L
H
H
H
NOP
L
H
H
L
BST
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
ILLEGAL
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Idle
H
×
×
×
×
×
×
DESL
NOP
L
H
H
H
NOP
NOP
L
H
H
L
BST
NOP
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
Bank and row active
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh
L
L
L
L
MODE
MRS
Mode register set
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