參數(shù)資料
型號(hào): HB52RD168DB
廠商: Hitachi,Ltd.
英文描述: 128 MB Unbuffered SDRAM S.O.DIMM(128MB 未緩沖同步DRAM DIMM)
中文描述: 128 MB的無緩沖內(nèi)存的SODIMM(128MB的未緩沖同步的DRAM內(nèi)存)
文件頁(yè)數(shù): 1/67頁(yè)
文件大?。?/td> 623K
代理商: HB52RD168DB
HB52RD168DB-D
128 MB Unbuffered SDRAM S.O.DIMM
16-Mword
×
64-bit, 100 MHz Memory Bus, 1-Bank Module
(16 pcs of 16 M
×
4 components)
PC100 SDRAM
ADE-203-990 (Z)
Preliminary, Rev. 0.0
Dec. 16, 1998
Description
The HB52RD168DB is a 16M
×
64
×
1 bank Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 16 pieces of 64-Mbit SDRAM (HM5264405DTB) sealed in TCP
package and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the
HB52RD168DB is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, the
HB52RD168DB makes high density mounting possible without surface mount technology. The
HB52RD168DB provides common data inputs and outputs. Decoupling capacitors are mounted beside
TCP on the module board.
Note:
Do not push the cover or drop the modules in order to protect from mechanical defects, which
would be electrical defects.
Features
Fully compatible with JEDEC standard outline unbuffered 8-byte S.O.DIMM
144-pin Zig Zag Dual tabs socket type
Outline: 67.60 mm (Length)
×
25.40 mm (Height)
×
3.80 mm (Thickness)
Lead pitch: 0.80 mm
3.3 V power supply
Clock frequency: 100 MHz
LVTTL interface
Data bus width:
×
64 Non parity
Single pulsed
RAS
4 Banks can operates simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length : 1/2/4/8/full page
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
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