參數(shù)資料
型號(hào)： HB52R168DB
廠(chǎng)商： Hitachi,Ltd.
英文描述： 128 MB Unbuffered SDRAM S.O.DIMM(128 MB 未緩沖同步DRAM S.O.DIMM)
中文描述： 128 MB的無(wú)緩沖內(nèi)存的SODIMM（128 MB的未緩沖同步內(nèi)存的SODIMM）
文件頁(yè)數(shù)： 17/57頁(yè)
文件大?。?/td> 860K
代理商： HB52R168DB
HB52R168DB-F
17
Column address strobe and write command [WRIT]:
This command starts a write operation. When the
burst write mode is selected, the column address and the bank select address (BA) become the burst write start
address. When the single write mode is selected, data is only written to the location specified by the column
address and the bank select address (BA).
Write with auto-precharge [WRIT A]:
This command automatically performs a precharge operation after a
burst write with a length of 1, 2, 4, or 8, or after a single write operation. When the burst length is full-page,
this command is illegal.
Row address strobe and bank activate [ACTV]:
This command activates the bank that is selected by bank
select address (BA) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank0 is
activated. When A12 is High and A13 is Low, bank1 is activated. When A12 is Low and A13 is High, bank2
is activated. When A12 and A13 are High, bank3 is activated.
Precharge selected bank [PRE]:
This command starts precharge operation for the bank selected by
A12/A13. If A12 and A13 are Low, bank0 is selected. If A12 is High and A13 is Low, bank1 is selected. If
A12 is Low and A13 is High, bank2 is selected. If A12 and A13 are High, bank3 is selected.
Precharge all banks [PALL]:
This command starts a precharge operation for all banks.
Refresh [REF/SELF]:
This command starts the refresh operation. There are two types of refresh operation,
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE0 truth table section.
Mode register set [MRS]:
The SDRAM module has a mode register that defines how it operates. The mode
register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the
mode register configuration. After power on, the contents of the mode register are undefined, execute the
mode register set command to set up the mode register.
DQMB Truth Table
CKE
Command
Symbol
n - 1
n
DQMB
Write enable/output enable
ENB
H
×
×
L
Write inhibit/output disable
Note:
H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
.
Read: I
DOD
is needed.
Write: I
DOD
is needed.
MASK
H
H
The SDRAM module can mask input/output data by means of DQMB During reading, the output buffer is set
to Low-Z by setting DQMB to Low, enabling data output. On the other hand, when DQMB is set to High, the
output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQMB to
Low. When DQMB is set to High, the previous data is held (the new data is not written). Desired data can be
masked during burst read or burst write by setting DQMB. For details, refer to the DQMB control section of
the SDRAM module operating instructions.
相關(guān)PDF資料
PDF描述
HB52R2569E2 2 GB Registered SDRAM DIMM(2GB 寄存同步DRAM DIMM)
HB52R329E22 256 MB Registered SDRAM DIMM(256 MB 寄存同步DRAM DIMM)
HB52R329E2 256 MB Registered SDRAM DIMM(256 MB 寄存同步DRAM DIMM)
HB52RD168DB 128 MB Unbuffered SDRAM S.O.DIMM(128MB 未緩沖同步DRAM DIMM)
HB52RD328DC 256 MB Unbuffered SDRAM S.O.DIMM(256 MB 未緩沖同步DRAM S.O.DIMM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HB52R168DB-10 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x64 SDRAM Module
HB52R168DB-10F 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x64 SDRAM Module
HB52R168DB-10FL 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x64 SDRAM Module
HB52R168DB-10L 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x64 SDRAM Module
HB52R329E22-A6F 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x72 SDRAM Module
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