參數(shù)資料
型號(hào)： GC4116
廠商： Electronic Theatre Controls, Inc.
英文描述： MULTI-STANDARD QUAD DUC CHIP
中文描述： 多標(biāo)準(zhǔn)四數(shù)字上芯片
文件頁(yè)數(shù)： 56/57頁(yè)
文件大?。?/td> 401K
代理商： GC4116
REV 1.0
APRIL 27, 2001
GC4116 REGISTER ASSIGNMENT QUICK REFERENCE GUIDE
.
Page
Address
Name
7(MSB)
6
5
4
3
2
1
0(LSB)
Suggested
Default
Global
0
Sync Mode
ONE_SHOT
USE_OS
OUTPUT_SYNC (SIA)
COUNTER_SYNC (SIA)
INT_SYNC (SIA)
E9 then 69
1
Int Mode
DIAG_SYNC (SIA)
DIAG
NOSYM
TEST
GAIN_SYNC
SPLIT_IQ
REAL
00
2
Int Gain
-
BIG_SHIFT
SCALE
09
3
Int Byte 0
INT[0:7]
07
4
Int Byte 1
-
INT[8:13]
00
5
Reset
GLOBAL
PAD_RESET
NOCK_RESET
RES_RESET
RESET_D
RESET_C
RESET_B
RESET_A
FF then 00
6
Counter Byte 0
CNT[0:7]
00
7
Counter Byte 1
CNT[7:15]
00
8
Chan A Sync
DITHER_SYNC (SIB)
NCO_SYNC (SIB)
PHASE_SYNC (SIB)
FREQ_SYNC (SIB)
5F
9
Chan B Sync
DITHER_SYNC (SIB)
NCO_SYNC (SIB)
PHASE_SYNC (SIB)
FREQ_SYNC (SIB)
5F
10
Chan C Sync
DITHER_SYNC (SIB)
NCO_SYNC (SIB)
PHASE_SYNC (SIB)
FREQ_SYNC (SIB)
5F
11
Chan D Sync
DITHER_SYNC (SIB)
NCO_SYNC (SIB)
PHASE_SYNC (SIB)
FREQ_SYNC (SIB)
5F
12
Flush
FLUSH_D (SIA)
FLUSH_C (SIA)
FLUSH_B (SIA)
FLUSH_A (SIA)
55
13
Miscellaneous
OS_MODE
4_OUT_MODE
DIS_CK_LOSS
CK2X_TEST
EXT_CK2X
CMPLX_OUT
MSB_INVERT
NO_AUTO_FL
80
14
Status
CK_LOSS
RES_OVFLW
SUMIO_OVFL
CHAN_OVFLW
RES_MISSED
RES_IN_RDY
CHAN_MISSD
CHAN_IN_RDY
00
15
Page
-
PAGE
00
Page 0
Frequency
and
Phase
A,B
16,17,18,19 FREQ_A
32 bit channel A tuning frequency, LSBs in 16, MSBs in 19,
FREQ = 2
32
F/F
CK
16 bit channel A phase, LSBs in 20, MSBs in 21, PHASE=2
16
P/2
π
32 bit channel B tuning frequency, LSBs in 24, MSBs in 27,
FREQ = 2
32
F/F
CK
16 bit channel B phase, LSBs in 28, MSBs in 29, PHASE=2
16
P/2
π
00000000
20,21
PHASE_A
0000
24,25,26,27 FREQ_B
00000000
28,29
PHASE_B
0000
30
Checksum
CHECKSUM
read only
31
Revision
REVISION
read only
Page 1
Frequency
and
Phase
A,B
16,17,18,19 FREQ_C
32 bit channel C tuning frequency, LSBs in 16, MSBs in 19,
FREQ = 2
32
F/F
CK
16 bit channel C phase, LSBs in 20, MSBs in 21, PHASE=2
16
P/2
π
32 bit channel D tuning frequency, LSBs in 24, MSBs in 27,
FREQ = 2
32
F/F
CK
16 bit channel D phase, LSBs in 28, MSBs in 29, PHASE=2
16
P/2
π
00000000
20,21
PHASE_C
0000
24,25,26,27 FREQ_D
00000000
28,29
PHASE_D
0000
Page 2
Input
Gain
16
GAIN_A
8 bit input gain (G) for channel A. GAIN = G/128
80
17
GAIN_B
8 bit input gain (G) for channel B. GAIN = G/128
80
18
GAIN_C
8 bit input gain (G) for channel C. GAIN = G/128S
80
19
GAIN_D
8 bit input gain (G) for channel D. GAIN = G/128
80
Page 3
Channel
Inputs
16,17
CHAN_A_I
Channel A Input Data, I-Half. LSBs in 16, MSBs in 17
00
18,19
CHAN_A_Q
Channel A Input Data, Q-Half. LSBs in 18, MSBs in 19
00
20,21
CHAN_B_I
Channel B Input Data, I-Half. LSBs in 20, MSBs in 21
00
22,23
CHAN_B_Q
Channel B Input Data, Q-Half. LSBs in 22, MSBs in 23
00
24,25
CHAN_C_I
Channel C Input Data, I-Half. LSBs in 24, MSBs in 25
00
26,27
CHAN_C_Q
Channel C Input Data, Q-Half. LSBs in 26, MSBs in 27
00
28,29
CHAN_D_I
Channel D Input Data, I-Half. LSBs in 28, MSBs in 29
00
30,31
CHAN_D_Q
Channel D Input Data, Q-Half. LSBs in 30, MSBs in 31
00
Page 4
Re-
sampler
Inputs
16,17
RES_A_I
Resampler A Input Data, I-Half. LSBs in 16, MSBs in 17
00
18,19
RES_A_Q
Resampler A Input Data, Q-Half. LSBs in 18, MSBs in 19
00
20,21
RES_B_I
Resampler B Input Data, I-Half. LSBs in 20, MSBs in 21
00
22,23
RES_B_Q
Resampler B Input Data, Q-Half. LSBs in 22, MSBs in 23
00
24,25
RES_C_I
Resampler C Input Data, I-Half. LSBs in 24, MSBs in 25
00
26,27
RES_C_Q
Resampler C Input Data, Q-Half. LSBs in 26, MSBs in 27
00
28,29
RES_D_I
Resampler D Input Data, I-Half. LSBs in 28, MSBs in 29
00
30,31
RES_D_Q
Resampler D Input Data, Q-Half. LSBs in 30, MSBs in 31
00
P
F
I
R
16-19
16-31
PFIR_A Taps
32 PFIR Coefficients for channel A. Load LSBs in even addresses, MSBs in odd addresses
20-23
16-31
PFIR_B Taps
32 PFIR Coefficients for channel B. Load LSBs in even addresses, MSBs in odd addresses
24-27
16-31
PFIR_C Taps
32 PFIR Coefficients for channel C. Load LSBs in even addresses, MSBs in odd addresses
28-31
16-31
PFIR_D Taps
32 PFIR Coefficients for channel D. Load LSBs in even addresses, MSBs in odd addresses
SYNC MODE
SYNC SOURCE
0
off (never asserted)
1
SIA or SIB, See each sync for (SIA) or (SIB)
2
TC (OS if USE_OS is set)
3
on (always active)
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