參數(shù)資料
型號(hào)： GC4116
廠商： Electronic Theatre Controls, Inc.
英文描述： MULTI-STANDARD QUAD DUC CHIP
中文描述： 多標(biāo)準(zhǔn)四數(shù)字上芯片
文件頁(yè)數(shù)： 46/57頁(yè)
文件大小： 401K
代理商： GC4116
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
19992001
GRAYCHIP,INC.
- 41 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
5.10
PFIR COEFFICIENT PAGES (PAGES 16 to 31)
The user programmable filter PFIR coefficients are stored using pages16 to 19 for channel A, pages 20 to 23 for channel B,
pages 24 to 27 for channel C, and pages 28 to 31 for channel D.
Table 10: PFIR Coefficient Pages
Coefficient h
0
is the first coefficient and coefficient h
31
is the center coefficient of the filter’s impulse response. The 16 bit 2’s
complement coefficients are stored in two bytes, least significant byte first, for example, the LSBs of coefficient 0 are stored in
address 16 and the MSBs in address 17.
TO LOAD A COEFFICIENT THE USER MUST WRITE THE LSBYTE FIRST FOLLOWED BY THE MSBYTE. Unknown
values will be written into the LSBs if the MSB is written first. The coefficient registers are read/write.
Address
Pages 16, 20, 24 or 28
Pages 17, 21, 25 or 29
Pages 18, 22, 26 or 30
Pages 19, 23, 27 or 31
Description
Description
Description
Description
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
h
0
LSBs (end tap)
h
0
MSBs (end tap)
h
1
LSBs
h
1
MSBs
h
2
LSBs
h
2
MSBs
h
3
LSBs
h
3
MSBs
h
4
LSBs
h
4
MSBs
h
5
LSBs
h
5
MSBs
h
6
LSBs
h
6
MSBs
h
7
LSBs
h
7
MSBs
h
8
LSBs
h
8
MSBs
h
9
LSBs
h
9
MSBs
h
10
LSBs
h
10
MSBs
h
11
LSBs
h
11
MSBs
h
12
LSBs
h
12
MSBs
h
13
LSBs
h
13
MSBs
h
14
LSBs
h
14
MSBs
h
15
LSBs
h
15
MSBs
h
16
LSBs
h
16
MSBs
h
17
LSBs
h
17
MSBs
h
18
LSBs
h
18
MSBs
h
19
LSBs
h
19
MSBs
h
20
LSBs
h
20
MSBs
h
21
LSBs
h
21
MSBs
h
22
LSBs
h
22
MSBs
h
23
LSBs
h
23
MSBs
h
24
LSBs
h
24
MSBs
h
25
LSBs
h
25
MSBs
h
26
LSBs
h
26
MSBs
h
27
LSBs
h
27
MSBs
h
28
LSBs
h
28
MSBs
h
29
LSBs
h
29
MSBs
h
30
LSBs
h
30
MSBs
h
31
LSBs (center tap)
h
31
MSBs (center tap)
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