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參數(shù)資料
| 型號： | GC4116 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MULTI-STANDARD QUAD DUC CHIP |
| 中文描述： | 多標(biāo)準(zhǔn)四數(shù)字上芯片 |
| 文件頁數(shù)： | 49/57頁 |
| 文件大?。?/td> | 401K |
| 代理商： | GC4116 |
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GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
19992001
GRAYCHIP,INC.
- 44 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
6.4
POWER CONSUMPTION
The power consumption is a function of the operating mode of the chip. The following equation estimates the typical power
supply current for the chip. Chip to chip variation is typically +/- 5%. The AC specification in Table 16 is the current tested for
during production test and represents the absolute maximum power supply current.
Where A is the number of active channels (0 to 4), N is the CIC decimation ratio, F
CK
is the clock rate, Nout is the number of
active output data pins, and Cout is the average capacitive load on each data pin. R is one if the resampler is active, and is 0 if
the resampler is off (RES_RESET=1 in address 5). The equation assumes random data transition density of 1 rising edge per
four clock cycles.
6.5
DC CHARACTERISTICS
Table 15: DC Operating Conditions (-40 to 85
°
C case unless noted)
PARAMETER
SYMBOL
V
PAD
= 3.0 to 3.6V
UNITS
TEST
LEVEL
MIN
MAX
Voltage input low
V
IL
0.8
V
IV
Voltage input high
V
IH
2.3
V
IV
Voltage output low (I
OL
= 2mA)
V
OL
0.5
V
IV
Voltage output high (I
OH
= -2mA)
V
OH
2.4
V
IV
Leakage current (V
IN
= 0V or V
PAD
)
Inputs or Outputs in tristate condition
| I
IN
|
1
uA
IV
Pullup current (V
IN
= 0V) (
TDI, TMS, TCK
)
| I
PU
|
5
35
uA
IV
Quiescent supply current, I
CORE
or I
PAD
(V
IN
=0 or V
IN
=V
PAD
, Address 0 = F0, LVDS=0)
I
CCQ
2
mA
IV
Data input capacitance (All inputs except
CK
)
C
IN
4 (typical)
pF
I
Clock input capacitance (
CK
input)
C
CK
13 (typical)
pF
I
Notes:
Currents are measured at nominal voltages, high temperature (85C).
Voltages are measured at low speed. Output voltages are measured with the indicated current load
Test Levels:
I. Controlled by design and process and not directly tested or recommended practice.
II. Verified on initial part evaluation.
III. 100% tested at room temperature, sample tested at hot and cold.
IV. 100% tested at hot, sample tested cold.
V. 100% tested at hot and cold.
I
PAD
(TYP)
V
PAD
(
)
F
CK
-------
4
N
out
(
)
C
out
(
)
=
I
CORE
(TYP)
V
CORE
2.5
------------
F
100
M
-------------
20
A 30
450
N
--------
+
15
R
+
+
mA
=
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