參數(shù)資料
型號(hào)： GC4116
廠商： Electronic Theatre Controls, Inc.
英文描述： MULTI-STANDARD QUAD DUC CHIP
中文描述： 多標(biāo)準(zhǔn)四數(shù)字上芯片
文件頁(yè)數(shù)： 27/57頁(yè)
文件大小： 401K
代理商： GC4116
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
19992001
GRAYCHIP,INC.
- 22 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
SIGNAL
DESCRIPTION
SCSTART
SERIAL CONTROLLER START
, active high input
The start pulse for the serial controller. Normally
connected to CHREQ or RREQ. Can only be high
for one CK cycle at a time.
SCCK 0,1
SERIAL CONTROLLER OUTPUT CLOCKS
,
active high or low outputs
These outputs provide two copies of a
programmable serial clock. Normally used to drive
both the serial clock port of a DSP, FPGA or ASIC
chip and the serial clock inputs of either the
resampler block (RSCK-A,B,C,D) or the channels
(SCK-A,B,C,D).
SCFS A,B,C,D
SERIAL
STROBES
, active high or low outputs
The frame strobe outputs of the serial controller.
They are normally connected either to the
resampler input frame strobes (RSFS-A,B,C,D) or
the channel input frame strobes (SFS-A,B,C,D) as
well as to a DSP, FPGA or ASIC chip’s serial
frame strobe input.
CONTROLLER
OUTPUT
FRAME
SUMI[0:21]
SUM IO INPUT DATA.
Active high inputs
The 22 bit two’s complement sum tree input
samples. New samples are clocked into the chip
on the rising edge of CK. The input data rate is
assumed to be equal to the clock rate.
SUMO[0:21]
SUM IO OUTPUT DATA
. Active high outputs
The 22 bit sum tree output data. The bits are
clocked out on the rising edge of the clock (
CK
).
Programmable two’s complement or offset binary.
QFLG
Q FLAG
. Active high output
This output is high to identify the imaginary half of
a complex sample. This is useful in complex
output mode where I and Q are multiplexed onto
the sum IO pins. QFLG is clocked out on the rising
edge of CK.
TMS,TCK,TDI,TDO
JTAG INTERFACE.
Active high input (
TCK
,
TMS
,
TDI
) and active
high tristate output (
TDO
) pins
The JTAG interface, see Section 3.15.
SIGNAL
DESCRIPTION
C[0:7]
CONTROL DATA I/O BUS
. Active high
bidirectional
This is the 8 bit control data I/O bus. Control
register data is loaded into the chip or read from
the chip through these pins. The chip will only
drive these pins when
CE
is low and
RD
is low and
WR
is high.
A[0:4]
CONTROL ADDRESS BUS
. Active high input
These pins are used to address the control
registers within the chip. Each of the control
registers within the chip are assigned a unique
address. A control register can be written to or
read from by having the page register set to the
appropriate page and then setting
A[0:4]
to the
register’s address.
RD
READ ENABLE
. Active low input
This pin enables the chip to output the contents of
the selected register on the
C[0:7]
pins when
CE
is also low.
WR
WRITE ENABLE
. Active low input
This pin enables the chip to write the value on the
C[0:7]
pins into the selected register when
CE
is
also low.
CE
CHIP ENABLE
. Active low input
This control strobe enables the read or write
operation. The contents of the register selected by
A[0:5]
will be output on
C[0:7]
when
RD
is low and
CE
is low.
If
WR
is low and
CE
is low, then the
selected register will be loaded with the contents
of
C[0:7].
WRMODE
WRITE MODE
. Active high input
This pin changes the write timing on the control
port so that the data need only be stable relative to
the rising edge of either
WR
or
CE
.
VCORE
CORE SUPPLY VOLTAGE
.
These pins are used to supply the core logic.
Nominally set at 2.5V.
VPAD
INTERFACE VOLTAGE
.
These pins are used to set the voltage I/O levels
for all pins. Nominally set at 3.3V. Still functional at
lower supplies but at reduced speed.
GND
GROUND.
TGND
THERMAL GROUND
These pins are used to extract heat from the die
and should be connected to the ground plane.
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