參數(shù)資料
型號: GC4116
廠商: Electronic Theatre Controls, Inc.
英文描述: MULTI-STANDARD QUAD DUC CHIP
中文描述: 多標準四數(shù)字上芯片
文件頁數(shù): 37/57頁
文件大?。?/td> 401K
代理商: GC4116
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
19992001
GRAYCHIP,INC.
- 32 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
5.5
CHANNEL INPUT PAGE (PAGE 3)
Page 3 is used to enter input data in the parallel mode (see PARALLEL_A,B,C and D in address of the IO control page).
ADDRESSES 16 to 31: Channel Inputs
The CHAN_INPUT_READY and CHAN_MISSED control bits in the status register (address 14) can be used as “handshake”
signals between the chip and the external processor providing the data. The external processor sets CHAN_INPUT_READY
after it has loaded the channel inputs into page 3. The chip will then clear CHAN_INPUT_READY when it has used the new
inputs. The external processor can monitor CHAN_INPUT_READY to determine when it is time to load new inputs. If the external
processor has not set CHAN_INPUT_READY when the chip wants to use the inputs, then it will set CHAN_MISSED to let the
external processor know that a handshake error has occurred and input samples have been missed.
The external processor can also use the CHREQ output as an interrupt to know new samples are needed.
ADDRESS
TYPE
NAME
DESCRIPTION
16
R/W
CHAN_A_I[0:7]
The 8 LSBs of Channel A’s I input
17
R/W
CHAN_A_I[8:15]
The 8 MSBs of Channel A’s I input
18
R/W
CHAN_A_QI[0:7]
The 8 LSBs of Channel A’s Q input
19
R/W
CHAN_A_Q[8:15]
The 8 MSBs of Channel A’s Q input
20
R/W
CHAN_B_I[0:7]
The 8 LSBs of Channel A’s I input
21
R/W
CHAN_B_I[8:15]
The 8 MSBs of Channel A’s I input
22
R/W
CHAN_B_QI[0:7]
The 8 LSBs of Channel A’s Q input
23
R/W
CHAN_B_Q[8:15]
The 8 MSBs of Channel A’s Q input
24
R/W
CHAN_C_I[0:7]
The 8 LSBs of Channel A’s I input
25
R/W
CHAN_C_I[8:15]
The 8 MSBs of Channel A’s I input
26
R/W
CHAN_C_QI[0:7]
The 8 LSBs of Channel A’s Q input
27
R/W
CHAN_C_Q[8:15]
The 8 MSBs of Channel A’s Q input
28
R/W
CHAN_D_I[0:7]
The 8 LSBs of Channel D’s I input
29
R/W
CHAN_D_I[8:15]
The 8 MSBs of Channel D’s I input
30
R/W
CHAN_D_QI[0:7]
The 8 LSBs of Channel D’s Q input
31
R/W
CHAN_D_Q[8:15]
The 8 MSBs of Channel D’s Q input
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