參數(shù)資料
型號(hào)： GC4116
廠商： Electronic Theatre Controls, Inc.
英文描述： MULTI-STANDARD QUAD DUC CHIP
中文描述： 多標(biāo)準(zhǔn)四數(shù)字上芯片
文件頁(yè)數(shù)： 26/57頁(yè)
文件大?。?/td> 401K
代理商： GC4116
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
19992001
GRAYCHIP,INC.
- 21 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
SIGNAL
DESCRIPTION
CK
INPUT CLOCK.
Active high input
The clock input to the chip. The
SUMI, RSTART,
SCSTART, SIA
and
SIB
input signals are clocked
into the chip on the rising edge of this clock. The
SUMO, CHREQ, RREQ, ROUT, ROCK, ROFS,
SCCK, SCFS and SO outputs are clocked out by
the rising edge of CK.
CK2X
DOUBLE RATE INPUT CLOCK.
Active high input
The chip uses an internally doubled clock for
normal processing. For test purposes the double
rate clock can be supplied externally using this
pin. Should be grounded for normal use.
SIA,
SIB
SYNC IN
. Active low input
The sync inputs to the chip. These syncs are
clocked into the chip on the rising edge of the input
clock (
CK
). All timers, accumulators, and control
counters are, or can be, synchronized to one of
SIA
or
SIB
.
SO
SYNC OUT
. Active low output
This signal is either a delayed version of the input
sync
SIA
, the sync counter’s terminal count (TC),
or a one-shot strobe. The
SO
signal is clocked out
of the chip on the rising edge of the input clock
(
CK
).
CHREQ
CHANNEL DATA REQUEST
,
programmable active high or low output
The chip requests new input data for the channels
by asserting this signal. CHREQ is clocked out of
the chip on the rising edge of CK and is one CK
cycle wide. The polarity of this signal is user
programmable. This signal is typically connected
to the RSTART input of the resampler, or the
SCSTART input of the serial controller. It can also
be used as a start pulse to dedicated circuitry or an
interrupt to a DSP chip.
SIN A,B,C,D
BIT SERIAL INPUT DATA,
Active high input
The bit serial input data for the four channels. The
I and Q halves of complex data are entered on the
same pin. Each time the chip asserts
CHREQ
(See above) the I-half is entered and then the
Q-half.
SCK A,B,C,D
BIT SERIAL DATA CLOCK
,
Active high or low input
The serial data bits are clocked into the chip by
these clocks. The active edge of these clocks are
user programmable.
SFS A,B,C,D
BIT SERIAL FRAME STROBE
,
Active high or low input
The bit serial word strobe. This strobe delineates
the 16 bit words, or 32 bit complex pair, within the
bit serial input stream. This strobe can be a pulse
at the beginning of each bit serial word, or can act
as a window enable which is active while the data
bits are active.
SIGNAL
DESCRIPTION
RREQ
RESAMPLER REQUEST
,
programmable active high or low output
The chip requests new input data for the
resampler by asserting this signal. RREQ is
clocked out of the chip on the rising edge of CK
and is one CK cycle wide. The polarity of this
signal is user programmable. This signal must be
connected to the SCSTART input of the serial
controller if the resampler is being used. It can
also be used as an interrupt to a DSP chip, or as a
start pulse to dedicated circuitry.
RSTART
RESAMPLER START
,
active high input
This input requests the resampler to send data.
Typically connected to CHREQ. RSTART is
clocked into the chip on the rising edge of CK and
can only be high for one CK cycle.
RIN A,B,C,D
RESAMPLER INPUT BIT SERIAL DATA,
Active high input
The bit serial input data for the resampler input.
The I and Q halves of complex data are entered on
the same pin, MSB to LSB, I-half followed by
Q-half.
RCK A,B,C,D
RESAMPLER INPUT SERIAL CLOCK
,
Active high or low input
The resampler serial data bits are clocked into the
chip by these clocks. The active edge of these
clocks are user programmable.
RFS A,B,C,D
RESAMPLER INPUT FRAME STROBE
,
Active high or low input
The resampler bit serial frame strobe. This strobe
delineates the 32 bit complex words within the bit
serial input stream. This strobe can be a pulse at
the beginning of each bit serial word, or can act as
a window enable which is active while the data bits
are active.
ROUT A,B,C,D
RESAMPLER OUTPUT BIT SERIAL DATA,
Active high output
The bit serial output data from the resampler. The
I and Q halves of complex data are transmitted on
the same pin, I followed by Q, 16 bits each, MSB
first.
ROCK 0,1
RESAMPLER OUTPUT SERIAL CLOCKS
,
programmable active high or low output
These outputs provide two copies of a
programmable serial clock. Normally used to drive
the serial clock inputs to the channels
(SCK-A,B,C,D).
ROFS 0,1
RESAMPLER OUTPUT FRAME STROBES
,
programmable active high or low output
The resampler outputs a single frame strobe
common to all outputs. Two copies of this signal
are provided for fan out. They are normally
connected to the channels (SFS-A,B,C,D).
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