參數(shù)資料
型號(hào)： GC4116
廠商： Electronic Theatre Controls, Inc.
英文描述： MULTI-STANDARD QUAD DUC CHIP
中文描述： 多標(biāo)準(zhǔn)四數(shù)字上芯片
文件頁(yè)數(shù)： 22/57頁(yè)
文件大?。?/td> 401K
代理商： GC4116
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
19992001
GRAYCHIP,INC.
- 17 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
3.12.1 Initializing Multiple GC4116 Chips
The multi-GC4116 initialization procedure assumes that
the SIA sync input pins of all GC4116 chips are tied together
and are connected to the SO output of the “master” chip, or
to a common sync source. The procedure is to:
(1) reset the chip by setting address 5, the reset register,
to 0xFF;
(2) configure the rest of the chip including setting the
INT_SYNC, RES_SYNC and FLUSH_(A,B,C,D) to be SIA,
the OS_MODE to be 1, and the OUTPUT_SYNC to be OS
(see Table 1);
(3) assert the SIA sync input by setting the ONE_SHOT
control bit high (or by setting the external SIA source low);
(4) release the global resets by setting address 5 to
0x00; and
(5) release the SIA sync by setting ONE_SHOT to 0 (or
the external SIA source high).
The global resets are asserted before configuring the
chip so that the operation of all of the pins, including the
directions of the bidirectional and tristate pins, will be
established before the global resets release them. The SIA
sync is asserted before releasing the global resets so that the
channels will remain in a reset state after the global resets
are released. All channels and the resampler will then start
synchronously by releasing the SIA sync. If there are multiple
chips which need synchronized, then synchronously
releasing the SIA sync to them all will force them all to be
synchronized.
The frequency, phase and gain of multiple chips can be
initialized by holding SIB low and then releasing it to all of the
chips at the same time.
3.12.2 Initializing Stand Alone GC4116 chips
The initialization sequence for a stand alone GC4116
chip is similar to the one for the multi-GC4116 procedure,
except that the ONE_SHOT is used to synchronize the chip,
not the SIA input sync. The procedure is to:
(1) reset the chip by setting address 5, the reset register,
to 0xFF;
(2) configure the rest of the chip including setting the
INT_SYNC, RES_SYNC and FLUSH_(A,B,C,D) to be
ONE_SHOT (mode 2) and the OS_MODE to be 1;
(3) assert the syncs by setting ONE_SHOT high;
(4) release the global resets by setting address 5 to
0x00; and
(5) release the syncs by setting ONE_SHOT to 0.
3.13
DATA LATENCY
The data latency through the chip is defined as the delay
from the rising edge of a step function input to the chip to the
rising edge of the step function as it leaves the chip. This
delay is dominated by the number of taps in each of the
filters. An estimate of the overall latency through the chip,
expressed as the number of CK clock cycles is:
(CIC latency = 2.5N) + (CFIR latency = 16N) +
(PFIR latency = N*PTAP) + (Resampler latency) + (Input
delay) + (Pipeline delay)
where N is the CIC interpolation ratio and PTAP is the
number of PFIR taps. PTAP is normally 63. Latency can be
reduced by using the NO_SYM_PFIR mode to shorten the
filter.
The Resampler latency, if the resampler is being used,
is approximately 2N*NMULT plus a resampler input sample
period and a resampler output period to allow for resampler
I/O buffering. The latency in the resampler can be minimized
by using the bypass configuration (See Section 3.7.7).
The Input delay is approximately two input sample
periods due to the double buffering in the serial input ports.
The Pipeline delay is approximately 40 clock cycles.
3.14
DIAGNOSTICS
The chip has an internal ramp generator which can be
used in place of the data inputs for diagnostics. An internal
checksum circuit generates a checksum of the output data to
verify the chip’s operation. See Section 7.12 for diagnostic
configurations and checksums.
Besides the internal diagnostics, the chip supports initial
board debug through special input and output tests. The
suggested procedure for bringing up the GC4116 chip on a
board is to first check the control interface by writing to the
control registers and reading them back. The diagnostics
described in Section 7.12 should be run next, followed by the
output and input tests described in Sections 7.13 and 7.14. If
these pass successfully, then the configuration customized
for the desired application should work.
3.15
JTAG
The GC4116 supports a four pin (TDI, TDO, TCK and
TMS) boundary scan interface. Contact GRAYCHIP to
receive the GC4116’s BSDL file.
相關(guān)PDF資料
PDF描述
GD37931 SINGLE PHASE MOULDED BRIDGES 0,8 AMP TO 1,5 AMP
GD39931 SINGLE PHASE MOULDED BRIDGES 0,8 AMP TO 1,5 AMP
GD40931 SINGLE PHASE MOULDED BRIDGES 0,8 AMP TO 1,5 AMP
GD75189 QUADRUPLE LINE RECEIVERS
GD75189A QUADRUPLE LINE RECEIVERS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GC4116-PB 功能描述:上下轉(zhuǎn)換器 4 Ch Narrowband DDC Monitor RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
GC4116-PBZ 功能描述:上下轉(zhuǎn)換器 4 Ch Narrowband DDC Monitor RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
GC-41259-02 制造商:Microsemi Corporation 功能描述:DIODE - Bulk
GC4-12F1 制造商:GC Electronics 功能描述:Lead Acid Rectangular 12V 4Ah Rechargeable
GC4130A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GC4130A Low Distortion AGC Amplifier
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*