參數(shù)資料
型號(hào)： GC4116
廠商： Electronic Theatre Controls, Inc.
英文描述： MULTI-STANDARD QUAD DUC CHIP
中文描述： 多標(biāo)準(zhǔn)四數(shù)字上芯片
文件頁(yè)數(shù)： 50/57頁(yè)
文件大小： 401K
代理商： GC4116
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
19992001
GRAYCHIP,INC.
- 45 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
6.6
AC CHARACTERISTICS
Table 16: AC Characteristics (-40 TO +85
o
C Case, unless noted)
PARAMETER
SYMBOL
2.3 V to 2.7 V
UNITS
TEST
LEVEL
MIN
MAX
Clock Frequency
F
CK
Note 1
100
MHz
IV
Clock low or high period
t
CKL/H
3
ns
IV
Clock Duty Cycle (t
CKH
as a percentage of the clock period)
70
%
II
Clock rise and fall times (V
IL
to V
IH
)
t
RF
2
ns
I
Input setup before
CK
goes high (
IN
or
SI
)
t
SU
2
ns
IV
Input hold time after
CK
goes high
t
HD
0.8
ns
IV
Serial Clock Frequency
F
SCK
0
100
MHz
IV
Serial Clock low or high period
t
SCKL/H
3
ns
IV
Serial Data Setup before SCK
t
SSU
2
ns
IV
Serial Data Hold from SCK
t
SHD
0.8
IV
Data output delay from rising edge of
CK
.
(
OUT, CHREQ, RSREQ, QFLG
or
SO
)
t
DLY
1
5
ns
IV
Output skew between
SCCK
and
SCFS
t
SCSK
-2
2.5
ns
IV
Output skew between
ROCK
and
ROFS or ROUT
t
ROSK
-2
2.5
ns
IV
JTAG Clock Frequency
F
JCK
0
40
MHz
IV
JTAG Clock low or high period
t
JCKL/H
10
ns
IV
JTAG Input (
TDI
or
TMS
) setup before
TCK
goes high
t
JSU
5
ns
IV
JTAG Input (
TDI
or
TMS
) hold time after
TCK
goes high
t
HD
10
ns
IV
JTAG output (
TDO
) delay from rising edge of
TCK
.
t
DLY
10
ns
IV
Control Setup before both
CE
,
WR
or
RD
go low (See section 3.1)
t
CSU
2
ns
IV
Control data setup during writes (edge mode). (See section 3.1)
t
EWCSU
4
ns
IV
Control hold after
CE
,
WR
or
RD
go high. (See section 3.1)
t
CHD
1
ns
IV
Control strobe (
CE
or
WR
) pulse width (Write operation). (See section 3.1)
t
CSPW
20
ns
IV
Control recovery time between reads or writes. (See section 3.1)
t
REC
20
ns
IV
Control output delay
CE
and
RD
low to
C
(Read Operation). (See section 3.1)
t
CDLY
12
ns
IV
Control tristate delay after
CE
and
RD
go high. (See section 3.1)
t
CZ
4
ns
I
Supply current
(F
CK
=100MHz, N=9, all channels active). (See section 6.4)
I
CORE
395
mA
IV
Notes:
1. The minimum clock rate must satisfy F
/(4N) > 10KHz, where N is the CIC interpolation ratio.
2. Timing between signals is measured from mid-voltage (V
PAD
/2) to mid-voltage. Output loading is a 50 Ohm transmission line.
Test Levels:
I. Controlled by design and process and not directly tested or recommended practice.
II. Verified on initial part evaluation.
III. 100% tested at room temperature, sample tested at hot and cold.
IV. 100% tested at hot, sample tested cold.
V. 100% tested at hot and cold.
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