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參數(shù)資料
| 型號(hào)： | GC4116 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MULTI-STANDARD QUAD DUC CHIP |
| 中文描述： | 多標(biāo)準(zhǔn)四數(shù)字上芯片 |
| 文件頁數(shù)： | 30/57頁 |
| 文件大?。?/td> | 401K |
| 代理商： | GC4116 |
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GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
19992001
GRAYCHIP,INC.
- 25 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
ADDRESS 3:
Interpolation Byte 0
, suggested default = 0x07
ADDRESS 4:
Interpolation Byte 1
, suggested default = 0x00
Where
INT
is equal to
N
-1. The chip interpolates the input data by a factor of 2
N
for real input data and 4
N
for complex input
data, where
N
ranges from 8 to 16384. This provides an interpolation range from 32 to 65,536 for complex input signals and 16
to 32,768 for real input signals. NOTE: The chip needs to be flushed each time the interpolation registers are changed. See
Section 5.8. Values of
N
exceeding 1448 should be avoided since they will cause overflow unless the input signal amplitude is
correspondingly reduced. For complex output the signal is decimated by two after the CIC and before the mixer. As a result, the
effective interpolation amount is only
N
/2, but the gain needs to be calculated for “
N
”. The interpolation factor applies to all
channels in the chip.
In the SPLIT_IQ mode (see Section 3.3.4 and bit 1, address 1), INT is set to
INT
=2
N
-1, where N ranges from 4 to 8192.
ADDRESS 5:
Reset Register
, Set to 0xff on power up.
The reset register powers up to the reset state of 0xff. The register should be set to 0xff during initialization, and then cleared
to begin operation. See Section 3.12 for initialization details.
BIT
TYPE
NAME
DESCRIPTION
0-7
R/W
INT
[0:7]
The LSBs of the interpolation control word INT. INT is N-1.
BIT
TYPE
NAME
DESCRIPTION
0-5
R/W
INT
[8:13]
The 6 MSBs of the interpolation control word INT. INT is N-1.
6,7
R/W
Unused
BIT
TYPE
NAME
DESCRIPTION
0 LSB
R/W
RESET_A
This bit resets channel A. It is set during power up. While in reset the channel
consumes very modest power (uWatts).
1
R/W
RESET_B
This bit resets channel B.
2
R/W
RESET_C
This bit resets channel C.
3
R/W
RESET_D
This bit resets channel D.
4
R/W
RESAMPLER_RESET
This bit resets the resampler.
5
R/W
NOCK_RESET
Allows output enables to flow through registers in output pads. Set on power up
so that all outputs are tristated at power up. The user should reset this bit when
ready for outputs to drive.
6
R/W
PAD_RESET
This bit resets the output formatter block.
7
R/W
GLOBAL_RESET
This bit powers down the chip.
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