參數(shù)資料
型號(hào)： GC4116
廠商： Electronic Theatre Controls, Inc.
英文描述： MULTI-STANDARD QUAD DUC CHIP
中文描述： 多標(biāo)準(zhǔn)四數(shù)字上芯片
文件頁(yè)數(shù)： 39/57頁(yè)
文件大?。?/td> 401K
代理商： GC4116
GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
19992001
GRAYCHIP,INC.
- 34 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice
5.7
I/O CONTROL PAGE (PAGE 5)
Page 5 controls the formatting and IO speed of channel and resampler inputs, resampler output, sumout and enables for
the various outputs. Page five registers are listed in the table below:
ADDRESS 16:
Channel Input Mode Register
, suggested default = 0x01
Table 7: IO Control Page Registers (Page 5)
ADDRESS
NAME
DESCRIPTION
16
Channel Input Mode
Channel input format (packed, clock and frame polarity, parallel or serial).
17
Resampler Input Mode
Resampler input format (packed, clock and frame polarity, parallel or serial).
18
Resampler Output Mode
Controls resampler output clock rate, sync, polarity, and frame polarity.
19
Sum IOMode
Sum IO path rounding, delay, shifting, and clear.
20
Serial Controller Modes
Controls request clock rate, sync, and polarity.
21
Serial Controller Frame
Count
Sets the serial controller’s frame length.
22
Serial Controller Frame
Delays A and B
Delay positions for serial controller frame strobes A and B.
23
Serial Controller Frame
Delays C and D
Delay positions for serial controller frame strobes C and D.
24
Output Enables
Output enables for sum, resampler, request, frame strobes, sync out, and
request polarities.
25
Resampler Clock Divider
Sets the clock rate for the resampler computations
26-31
Unused
BIT
TYPE
NAME
DESCRIPTION
0 LSB
R/W
PACKED
Puts the channel serial inputs into the 32 bit transfer mode where each complex
pair is packed into 32 bit words. The complex pair is formatted as I word in the
upper 16 bits and the Q word in the lower 16 bits. Each word is formatted as
MSB first.
1
R/W
Unused
2
R/W
SCK_POL
The
SIN
Input bits and
SFS
frame strobes are clocked in on the trailing edge of
SCK when this bit is set. The rising edge is used when this bit is low.
3
R/W
SFS_POL
The
SFS
signal is treated as active low when this bit is set. Otherwise the signal
is treated as active high.
4
R/W
PARALLEL_A
The parallel/Serial control for channel input A. When low input for channel A is
taken from the serial port. When high it is taken from the channel input page
registers.
5
R/W
PARALLEL_B
The parallel/Serial control for channel B.
6
R/W
PARALLEL_C
The parallel/Serial control for channel C.
7
R/W
PARALLEL_D
The parallel/Serial control for channel D.
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