- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381841 > FDC37C666GT (STANDARD MICROSYSTEMS CORP) High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers PDF資料下載
參數(shù)資料
| 型號： | FDC37C666GT |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers |
| 中文描述： | 1 Mbps, IDE COMPATIBLE, FLOPPY DISK DRIVE CONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 96/152頁 |
| 文件大?。?/td> | 621K |
| 代理商： | FDC37C666GT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁當(dāng)前第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁
96
EPP DATA PORT 3
ADDRESS OFFSET = 07H
The EPP Data Port 3 is located at an offset of
'07H' from the base address. Refer to EPP
DATA PORT 0 for a description of operation.
This register is only available in EPP mode.
EPP 1.9 OPERATION
When the EPP mode is selected in the
configuration register, the standard and bi-
directional modes are also available. If no EPP
Read, Write or Address cycle is currently
executing, then the PDx bus is in the standard or
bi-directional mode, and all output signals
(STROBE, AUTOFD, INIT) are as set by the
SPP Control Port and direction is controlled by
PCD of the Control port.
In EPP mode, the system timing is closely
coupled to the EPP timing. For this reason, a
watchdog timer is required to prevent system
lockup. The timer indicates if more than 10usec
have elapsed from the start of the EPP cycle
(nIOR or nIOW asserted) to nWAIT being
deasserted (after command). If a time-out
occurs, the current EPP cycle is aborted and the
time-out condition is indicated in Status bit 0.
During an EPP cycle, if STROBE is active, it
overrides the EPP write signal forcing the PDx
bus to always be in a write mode and the
nWRITE signal to always be asserted.
Software Constraints
Before an EPP cycle is executed, the software
must ensure that the control register bit PCD is
a logic "0" (ie a 04H or 05H should be written to
the Control port). If the user leaves PCD as a
logic "1", and attempts to perform an EPP write,
the chip is unable to perform the write (because
PCD is a logic "1") and will appear to perform an
EPP read on the parallel bus, no error is
indicated.
EPP 1.9 Write
The timing for a write operation (address or
data) is shown in timing diagram EPP Write
Data or Address cycle. IOCHRDY is driven
active low at the start of each EPP write and is
released when it has been determined that the
write cycle can complete. The write cycle can
complete under the following circumstances:
1.
If the EPP bus is not ready (nWAIT is active
low) when nDATASTB or nADDRSTB goes
active then the write can complete when
nWAIT goes inactive high.
2.
If the EPP bus is ready (nWAIT is inactive
high) then the chip must wait for it to go
active low before changing the state of
nDATASTB, nWRITE or nADDRSTB. The
write can complete once nWAIT is
determined inactive.
Write Sequence of operation
1.
The host selects an EPP register, places
data on the SData bus and drives nIOW
active.
2.
The chip drives IOCHRDY inactive (low).
3.
If WAIT is not asserted, the chip must wait
until WAIT is asserted.
4.
The chip places address or data on PData
bus, clears PDIR, and asserts nWRITE.
5.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus contains valid
information, and the WRITE signal is valid.
6.
Peripheral deasserts nWAIT, indicating that
any setup requirements have been satisfied
and the chip may begin the termination
phase of the cycle.
7.
a)
The chip deasserts nDATASTB or
nADDRSTRB, this marks the beginning
of the termination phase. If it has not
already done so, the peripheral should
latch the information byte now.
b)
The chip latches the data from the
SData bus for the PData bus and
asserts (releases) IOCHRDY allowing
the host to complete the write cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FDC37C67X | ENHANCED SUPER I/O CONTROLLER WITH FAST IR |
| FDC37C957FR | ULTRA I/O CONTROLLER FOR PORTABLE APPLICATIONS |
| FDC37M600 | ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT |
| FDC37M601 | ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT |
| FDC37M602 | ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FDC37C669 | 制造商:SMSC 制造商全稱:SMSC 功能描述:PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support |
| FDC37C669_07 | 制造商:SMSC 制造商全稱:SMSC 功能描述:PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support |
| FDC37C669FRQFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| FDC37C669FRTQFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| FDC37C669-MS | 功能描述:輸入/輸出控制器接口集成電路 Super I/O Controller- Pb Free RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。