參數(shù)資料
型號： FDC37C666GT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 存儲控制器/管理單元
英文描述： High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
中文描述： 1 Mbps, IDE COMPATIBLE, FLOPPY DISK DRIVE CONTROLLER, PQFP100
封裝： QFP-100
文件頁數(shù)： 34/152頁
文件大?。?/td> 621K
代理商： FDC37C666GT
34
Table 13 - Data Rates
DRATESEL
1
0
1
0
0
1
0
Table 14 - Default Precompensation Delays
PRECOMPENSATION
MAIN STATUS REGISTER
Address 3F4 READ ONLY
The Main Status Register is a read-only register
and indicates the status of the disk controller.
The Main Status Register can be read at any
time. The MSR indicates when the disk
controller is ready to receive data via the Data
Register. It should be read before each byte
transferring to or from the data register except in
DMA mode. NO delay is required when reading
the MSR after a data transfer.
BIT 0 - 3 DRV x BUSY
These bits are set to 1s when a drive is in the
seek portion of a command, including implied
and overlapped seeks and recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in
progress. This bit will go active after the
command byte has been accepted and goes
inactive at the end of the results phase. If there
is
no
result
phase
commands), this bit is returned to a 0 after the
last command byte.
(Seek,
Recalibrate
BIT 5 NON-DMA
This mode is selected in the SPECIFY
command and will be set to a 1 during the
execution phase of a command. This is for
polled data transfers and helps differentiate
between the data transfer phase and the reading
of result bytes.
BIT 6 DIO
Indicates the direction of a data transfer once a
RQM is set. A 1 indicates a read and a 0
indicates a write is required.
BIT 7 RQM
Indicates that the host can transfer data if set to
a 1. No access is permitted if set to a 0.
DATA RATE
MFM
1 Mbps
500 Kbps
300 Kbps
250 Kbps
FM
Illegal
250 Kbps
150 Kbps
125 Kbps
1
0
1
DATA RATE
1 Mbps
500 Kbps
300 Kbps
250 Kbps
DELAYS
41.67 ns
125 ns
125 ns
125 ns
7
6
5
4
3
2
1
0
RQM
DIO
NON
DMA
CMD
BUSY
DRV3
BUSY
DRV2
BUSY
DRV1
BUSY
DRV0
BUSY
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