參數(shù)資料
型號： FDC37C666GT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 存儲控制器/管理單元
英文描述： High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
中文描述： 1 Mbps, IDE COMPATIBLE, FLOPPY DISK DRIVE CONTROLLER, PQFP100
封裝： QFP-100
文件頁數(shù)： 64/152頁
文件大?。?/td> 621K
代理商： FDC37C666GT
64
Read Deleted Data
This command is the same as the Read Data
command, only it operates on sectors that
contain a Deleted Data Address Mark at the
beginning of a Data Field.
Table 26 describes the effect of the SK bit on
the Read Deleted Data command execution and
results.
Except where noted in Table 26, the C or R
value of the sector address is automatically
incremented (see Table 27).
Table 26 - Skip Bit vs. Read Deleted Data Command
DATA ADDRESS
MARK TYPE
ENCOUNTERED
SECTOR
READ
Normal Data
Yes
SK BIT
VALUE
RESULTS
CM BIT OF
ST2 SET
Yes
DESCRIPTION
OF RESULTS
Address not
incremented.
Next sector not
searched for.
Normal
termination.
Normal
termination.
Sector not read
("skipped").
Normal
termination.
0
0
1
1
Deleted Data
Normal Data
Deleted Data
Yes
No
Yes
No
Yes
No
Read A Track
This command is similar to the Read Data
command except that the entire data field is
read continuously from each of the sectors of a
track. Immediately after encountering a pulse
on the nINDEX pin, the FDC starts to read all
data fields on the track as continuous blocks of
data without regard to logical sector numbers. If
the FDC finds an error in the ID or DATA CRC
check bytes, it continues to read data from the
track and sets the appropriate error bits at the
end of the command. The FDC compares the
ID information read from each sector with the
specified value in the command and sets the
ND flag of Status Register 1 to a "1" if there is
no comparison. Multi-track or skip operations
are not allowed with this command. The MT
and SK bits (bits D7 and D5 of the first
command byte respectively) should always be
set to "0".
This command terminates when the EOT
specified number of sectors has not been read.
If the FDC does not find an ID Address Mark on
the diskette after the second occurrence of a
pulse on the IDX pin, then it sets the IC code in
Status
Register
0
termination), sets the MA bit in Status Register
1 to "1", and terminates the command.
to
"01"
(abnormal
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