參數(shù)資料
型號(hào): FDC37C666GT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
中文描述: 1 Mbps, IDE COMPATIBLE, FLOPPY DISK DRIVE CONTROLLER, PQFP100
封裝: QFP-100
文件頁(yè)數(shù): 12/152頁(yè)
文件大?。?/td> 621K
代理商: FDC37C666GT
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12
DESCRIPTION OF PIN FUNCTIONS
BUFFER
TYPE
nCTS1,
nCTS2
PIN NO.
82,92
NAME
SYMBOL
DESCRIPTION
nClear to Send
I
Active low Clear to Send inputs for primary
and secondary serial ports. Handshake
signal which notifies the UART that the
modem is ready to receive data. The CPU
can monitor the status of nCTS signal by
reading bit 4 of Modem Status Register
(MSR). A nCTS signal state change from
low to high after the last MSR read will set
MSR bit 0 to a 1. If bit 3 of Interrupt Enable
Register is set, the interrupt is generated
when nCTS changes state. The nCTS
signal has no effect on the transmitter.
Note: Bit 4 of MSR is the complement of
nCTS.
Active low Data Set Ready inputs for
primary and secondary serial ports.
Handshake signal which notifies the UART
that the modem is ready to establish the
communication link. The CPU can monitor
the status of nDSR signal by reading bit 5 of
Modem Status Register (MSR). A nDSR
signal state change from low to high after
the last MSR read will set MSR bit 1 to a 1.
If bit 3 of Interrupt Enable Register is set,
the interrupt is generated when nDSR
changes state. Note: Bit 5 of MSR is the
complement of nDSR.
Active low Data Carrier Detect inputs for
primary and secondary serial ports.
Handshake signal which notifies the UART
that carrier signal is detected by the
modem. The CPU can monitor the status of
nDCD signal by reading bit 7 of Modem
Status Register (MSR). A nDCD signal
state change from low to high after the last
MSR read will set MSR bit 3 to a 1. If bit 3
of Interrupt Enable Register is set, the
interrupt is generated when nDCD changes
state. Note: Bit 7 of MSR is the
complement of nDCD.
80,90
nData Set Ready nDSR1,
nDSR2
I
85,87
nData Carrier
Detect
nDCD1,
nDCD2
I
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