參數(shù)資料
型號: FDC37C666GT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 存儲控制器/管理單元
英文描述: High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
中文描述: 1 Mbps, IDE COMPATIBLE, FLOPPY DISK DRIVE CONTROLLER, PQFP100
封裝: QFP-100
文件頁數(shù): 76/152頁
文件大小: 621K
代理商: FDC37C666GT
76
PARALLEL PORT FLOPPY DISK CONTROLLER
In this mode, the Floppy Disk Control signals
are available on the parallel port pins. When
this mode is selected, the parallel port is not
available. There are two modes of operation,
PPFD1 and PPFD2. These modes can be
selected in Configuration Register 4. PPFD1
has only drive 1 on the parallel port pins; PPFD2
has drive 0 and 1 on the parallel port pins.
PPFD1:
Drive 1 is on the Parallel port pins
Drive 2 is on the FDC pins*
Drive 3 is on the FDC pins*
Drive 0 is on the FDC pins
PPFD2:
Drive 0 is on the Parallel port
pins
Drive 1 is on the Parallel port pins
Drive 2 is on the FDC pins*
Drive 3 is on the FDC pins*
* If ECP is selected, then direct support for
drives 2 and 3 is not available. Drives 2 and 3
are available using external decoders.
When the PPFDC is selected the following pins
are set as follows:
1.
nDS2/PDIR (pin 98): not ECP = high-Z,
ECP = high
A10/nDS3 (pin 97): high-Z, A10 = to
internal logic.
nMTR2/nPDACK (pin 96): high-Z
2.
3.
4.
nMTR3/PDRQ (pin 99): not ECP = high-Z,
ECP & dmaEn = 0, ECP & not dmaEn =
high-Z
PINTR: not active, this is hi-Z or Low
depending on settings.
5.
The following parallel port pins are read as
follows by a read of the parallel port register:
1.
Data Register (read) = last Data Register
(write)
Control Register are read as "cable not
connected" STROBE, AUTOFD and SLC =
0 and nINIT = 1;
Status Register reads: nBUSY = 0, PE = 0,
SLCT = 0, nACK = 1, nERR = 1.
2.
3.
The following FDC pins are all in the high
impedence state when the PPFDC is actually
selected by the drive select register:
1.
nWDATA, DENSEL, nHDSEL, nWGATE,
nDIR, nSTEP, nDS1, nDS0, nMTRO,
nMTR1.
2.
If PPFDx is selected, then the parallel port
can not be used as a parallel port until
"Normal" mode is selected.
The FDC signals are muxed onto the Parallel
Port pins as shown in Table 33:
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