參數(shù)資料
型號： FDC37C666GT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 存儲控制器/管理單元
英文描述： High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
中文描述： 1 Mbps, IDE COMPATIBLE, FLOPPY DISK DRIVE CONTROLLER, PQFP100
封裝： QFP-100
文件頁數(shù)： 17/152頁
文件大小： 621K
代理商： FDC37C666GT
17
DESCRIPTION OF PIN FUNCTIONS
BUFFER
TYPE
IDED7
I/O24
PIN NO.
22
NAME
SYMBOL
DESCRIPTION
IDE Data Bit 7
IDE data bit 7 in the AT mode. IDED7
transfers data at I/O addresses 1F0H-1F7H
(R/W), 3F6 (R/W), 3F7(W). IDED7 should
be connected to IDE data bit 7. The
FDC37C665GT functions as a buffer
transferring data bit 7 between the IDE
device and the host. During I/O read of
3F7H, IDED7 is the FDC disk change bit. In
the XT mode, IDE7 is not used.
MISCELLANEOUS
I
58
Power Good
PWRGD
FDC37C665GT (Motherboard Mode): This
input indicates that the power (V
CC
) is valid.
For device operation, PWRGD must be
active. When PWRGD is inactive, all inputs
to the FDC37C665GT are disconnected and
put in a low power mode, all outputs are put
into high impedance. The contents of all
registers are preserved as long as V
CC
has a
valid value. The driver current drain in this
mode drops to ISTBY - standby current.
This input has a weak pullup resistor to V
CC
.
nGame Port
Chip Select
nGAMECS
PADCF
O4
I
FDC37C666GT (Adapter Mode): This is the
Game Port Chip Select output - active low.
It will go active when the I/O address is
201H.
FDC37C666GT (Adapter Mode): Parallel
Port Mode Control. Refer to FDC37C666GT
hardware
configuration
information. Read and latched during reset
active.
The external connection for a parallel
resonant 24 MHz crystal. A CMOS
compatible oscillator is required if crystal is
not used.
24 MHz crystal. If an external clock is used,
this pin should not be connected. This pin
should not be used to drive any other
drivers.
for
more
20
CLOCK 1
X1/CLK1
ICLK
21
CLOCK 2
X2/CLK2
OCLK
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