參數(shù)資料
型號: FDC37C666GT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 存儲控制器/管理單元
英文描述: High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
中文描述: 1 Mbps, IDE COMPATIBLE, FLOPPY DISK DRIVE CONTROLLER, PQFP100
封裝: QFP-100
文件頁數(shù): 84/152頁
文件大?。?/td> 621K
代理商: FDC37C666GT
84
associated with the particular character in the
FIFO it applies to. This error is indicated when
the associated character is at the top of the
FIFO.
Bit 3
Framing Error (FE). Bit 3 indicates that the
received character did not have a valid stop bit.
Bit 3 is set to a logic "1" whenever the stop bit
following the last data bit or parity bit is detected
as a zero bit (Spacing level). The FE is reset to
a logic "0" whenever the Line Status Register is
read. In the FIFO mode this error is associated
with the particular character in the FIFO it
applies to. This error is indicated when the
associated character is at the top of the FIFO.
The Serial Port will try to resynchronize after a
framing error. To do this, it assumes that the
framing error was due to the next start bit, so it
samples this 'start' bit twice and then takes in
the 'data'.
Bit 4
Break Interrupt (BI). Bit 4 is set to a logic "1"
whenever the received data input is held in the
Spacing state (logic "0") for longer than a full
word transmission time (that is, the total time of
the start bit + data bits + parity bits + stop bits).
The BI is reset after the CPU reads the contents
of the Line Status Register. In the FIFO mode
this error is associated with the particular
character in the FIFO it applies to. This error is
indicated when the associated character is at
the top of the FIFO. When break occurs only
one zero character is loaded into the FIFO.
Restarting after a break is received, requires the
serial data (RXD) to be logic "1" for at least 1/2
bit time.
Note: Bits 1 through 4 are the error conditions
that produce a Receiver Line Status Interrupt
whenever any of the corresponding conditions
are detected and the interrupt is enabled.
Bit 5
Transmitter Holding Register Empty (THRE). Bit
5 indicates that the Serial Port is ready to accept
a new character for transmission. In addition,
this bit causes the Serial Port to issue an
interrupt when the Transmitter Holding Register
interrupt enable is set high. The THRE bit is set
to a logic "1" when a character is transferred
from the Transmitter Holding Register into the
Transmitter Shift Register. The bit is reset to
logic "0" whenever the CPU loads the
Transmitter Holding Register. In the FIFO mode
this bit is set when the XMIT FIFO is empty, it is
cleared when at least 1 byte is written to the
XMIT FIFO. Bit 5 is a read only bit.
Bit 6
Transmitter Empty (TEMT). Bit 6 is set to a
logic "1" whenever the Transmitter Holding
Register (THR) and Transmitter Shift Register
(TSR) are both empty. It is reset to logic "0"
whenever either the THR or TSR contains a data
character. Bit 6 is a read only bit. In the FIFO
mode this bit is set whenever the THR and TSR
are both empty,
Bit 7
This bit is permanently set to logic "0" in the 450
mode. In the FIFO mode, this bit is set to a
logic "1" when there is at least one parity error,
framing error or break indication in the FIFO.
This bit is cleared when the LSR is read if there
are no subsequent errors in the FIFO.
MODEM STATUS REGISTER (MSR)
Address
Offset
READ/WRITE
=
6H,
DLAB
=
X,
This 8 bit register provides the current state of
the control lines from the MODEM (or peripheral
device). In addition to this current state
information, four bits of the MODEM Status
Register (MSR) provide change information.
These bits are set to logic "1" whenever a
control input from the MODEM changes state.
They are reset to logic "0" whenever the
MODEM Status Register is read.
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