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參數資料
| 型號： | FDC37C666GT |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers |
| 中文描述： | 1 Mbps, IDE COMPATIBLE, FLOPPY DISK DRIVE CONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數： | 83/152頁 |
| 文件大?。?/td> | 621K |
| 代理商： | FDC37C666GT |
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83
Bit 0
This bit controls the Data Terminal Ready
(nDTR) output. When bit 0 is set to a logic "1",
the nDTR output is forced to a logic "0". When
bit 0 is a logic "0", the nDTR output is forced to
a logic "1".
Bit 1
This bit controls the Request To Send (nRTS)
output. Bit 1 affects the nRTS output in a
manner identical to that described above for bit
0.
Bit 2
This bit controls the Output 1 (OUT1) bit. This
bit does not have an output pin and can only be
read or written by the CPU.
Bit 3
Output 2 (OUT2). This bit is used to enable an
UART interrupt. When OUT2 is a logic "0", the
serial port interrupt output is forced to a high
impedance state - disabled. When OUT2 is a
logic "1", the serial port interrupt outputs are
enabled.
Bit 4
This bit provides the loopback feature for
diagnostic testing of the Serial Port. When bit 4
is set to logic "1", the following occur:
1. The TXD is set to the Marking State(logic
"1").
2. The
receiver
Serial
disconnected.
3. The output of the Transmitter Shift Register
is "looped back" into the Receiver Shift
Register input.
4. All MODEM Control inputs (nCTS, nDSR,
nRI and nDCD) are disconnected.
5. The four MODEM Control outputs (nDTR,
nRTS, and OUT2) are internally connected
to the four MODEM Control inputs.
6. The Modem Control output pins are forced
inactive high.
7. Data that is transmitted is immediately
received.
Input
(RXD)
is
This feature allows the processor to verify the
transmit and receive data paths of the Serial
Port. In the diagnostic mode, the receiver and
the transmitter interrupts are fully operational.
The MODEM Control Interrupts are also
operational but the interrupts' sources are now
the lower four bits of the MODEM Control
Register instead of the MODEM Control inputs.
The interrupts are still controlled by the Interrupt
Enable Register.
Bits 5 through 7
These bits are permanently set to logic zero.
LINE STATUS REGISTER (LSR)
Address
Offset
READ/WRITE
=
5H,
DLAB
=
X,
Bit 0
Data Ready (DR). It is set to a logic "1"
whenever a complete incoming character has
been received and transferred into the Receiver
Buffer Register or the FIFO. Bit 0 is reset to a
logic "0" by reading all of the data in the Receive
Buffer Register or the FIFO.
Bit 1
Overrun Error (OE). Bit 1 indicates that data in
the Receiver Buffer Register was not read before
the next character was transferred into the
register,
thereby
destroying
character. In FIFO mode, an overrun error will
occur only when the FIFO is full and the next
character has been completely received in the
shift register, the character in the shift register is
overwritten but not transferred to the FIFO. The
OE indicator is set to a logic "1" immediately
upon detection of an overrun condition, and
reset whenever the Line Status Register is read.
the
previous
Bit 2
Parity Error (PE). Bit 2 indicates that the
received data character does not have the
correct even or odd parity, as selected by the
even parity select bit. The PE is set to a logic
"1" upon detection of a parity error and is reset
to a logic "0" whenever the Line Status Register
is read. In the FIFO mode this error is
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相關代理商/技術參數 |
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| FDC37C669 | 制造商:SMSC 制造商全稱:SMSC 功能描述:PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support |
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| FDC37C669FRQFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| FDC37C669FRTQFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| FDC37C669-MS | 功能描述:輸入/輸出控制器接口集成電路 Super I/O Controller- Pb Free RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
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