參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 91/132頁
文件大小： 0K
描述： BOARD EVAL FOR ADUC7036
設計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標準包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 61 of 132
POWER SUPPLY SUPPORT CIRCUITS
The ADuC7036 incorporates two on-chip low dropout (LDO)
regulators that are driven directly from the battery voltage to
generate a 2.6 V internal supply. This 2.6 V supply is then used
as the supply voltage for the ARM7 MCU and the peripherals,
including the on-chip precision analog circuits.
The digital LDO functions with two output capacitors (2.2 μF
and 0.1 μF) in parallel on REG_DVDD, whereas the analog LDO
functions with an output capacitor (0.47 μF) on REG_AVDD.
The ESR of the output capacitor affects stability of the LDO
control loop. An ESR of 5 Ω or less for frequencies greater than
32 kHz is recommended to ensure the stability of the regulators.
In addition, the power-on reset (POR), power supply monitor
(PSM), and low voltage flag (LVF) functions are integrated to
ensure safe operation of the MCU, as well as continuous
monitoring of the battery power supply.
The POR circuit is designed to operate with a VDD (0 V to 12 V)
power-on time of greater than 100 μs. It is, therefore, recom-
mended that the external power supply decoupling components
be carefully selected to ensure that the VDD supply power-on
time can always be guaranteed to be greater than 100 μs, regardless
of the VBAT power-on conditions. The series resistor and
decoupling capacitor combination on VDD should be chosen
to result in an RC time constant of at least 100 μs (for example,
10 Ω and 10 μF, as shown on Figure 60).
As shown in Figure 29, when the supply voltage on VDD reaches
a typical operating voltage of 3 V, a POR signal keeps the ARM
core in reset state for 20 ms. This ensures that the regulated
power supply voltage (REG_DVDD) applied to the ARM core
and associated peripherals is greater than the minimum oper-
ational voltage, thereby guaranteeing full functionality. A POR
flag is set in the RSTSTA MMR to indicate a POR event has
occurred.
The ADuC7036 also features a PSM function. When enabled
through HVCFG0[3], the PSM continuously monitors the voltage
at the VDD pin. If this voltage drops below 6 V typical, the PSM
flag is automatically asserted and can generate a system interrupt
if the high voltage IRQ is enabled via IRQEN[16] or FIQEN[16].
An example of this operation is shown in Figure 29.
At voltages below the POR level, an additional low voltage flag
can be enabled (HVCFG0[2]). This flag can be used to indicate
that the contents of the SRAM remain valid after a reset event.
The operation of the low voltage flag is shown in Figure 29. When
HVCFG0[2] is enabled, the status of this bit can be monitored
via HVMON[3]. If the HVCFG0[2] bit is set, the SRAM contents
are valid. If this bit is cleared, the SRAM contents may become
corrupted.
VDD
12V
3V TYP
2.6V
20ms TYP
PSM TRIP 6V TYP
POR TRIP 3V TYP
LVF TRIP 2.1V TYP
REG_DVDD
POR_TRIP
RESET_CORE
(INTERNAL SIGNAL)
ENABLE_PSM
ENABLE_LVF
07
47
4-
02
8
Figure 29. Typical Power-On Cycle
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