參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 103/132頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7036
設(shè)計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 72 of 132
T0
SYNC
T1
SYNC
T2
SYNC
T3
SYNC
T4
SYNC
T0
T1
T2
T3
T4
T0IRQ
T1IRQ
T2IRQ
T3IRQ
WdRst
T4IRQ
T0 REG
USER
MMR
INTERFACE
T1 REG
T2 REG
T3 REG
T4 REG
CORE
CLOCK
ARM7TDMI
AMBA
LOW
POWER
OSCILLATOR
HIGH
PRECISION
OSCILLATOR
GPIO
XTAL
0
1
2
4
AMBA
TIMER BLOCK
07
47
4-
0
58
Figure 33. Timer Block Diagram
UNSYNCHRONIZED
SIGNAL
SYNCHRONIZED
SIGNAL
TIMER 2
LOW POWER
CLOCK DOMAIN
SYNCHRONIZER
FLIP-FLOPS
CORE CLOCK
(FCORE)
DOMAIN
TARGET_CLOCK
07
47
4-
05
9
Figure 34. Synchronizer for Signals Crossing Clock Domains
As shown in Figure 33, the MMR logic and core timer logic
reside in separate and asynchronous clock domains. Any data
coming from the MMR core clock domain and being passed to
the internal timer domain must be synchronized to the internal
timer clock omain to ensure it is latched correctly into the core
timer clock domain. This is achieved by using two flip-flops as
shown in Figure 34 to not only synchronize but also to double
buffer the data and thereby ensuring data integrity in the timer
clock domain.
As a result of the synchronization block, while timer control
data is latched almost immediately (with the fast, core clock) in
the MMR clock domain, this data in turn will not reach the core
timer logic for at least two periods of the selected internal timer
domain clock.
PROGRAMMING THE TIMERS
Understanding synchronization across timer domains also
requires that the user code carefully programs the timers when
stopping or starting them. The recommended code controls the
timer block when stopping and starting the timers and when
using different clock domains. This can critical, especially if
timers are enabled to generate an IRQ or FIQ exception; Timer2
is used as an example.
Halting Timer2
When halting Timer2, it is recommended that the IRQEN
bit for Timer2 be masked (using IRQCLR). This prevents
unwanted IRQs from generating an interrupt in the MCU
before the T2CON control bits have been latched in the Timer2
internal logic.
IRQCLR = WAKEUP_TIMER_BIT;
//Masking interrupts
T2CON=0x00;
//Halting the timer
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