參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 42/132頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7036
設(shè)計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 17 of 132
Pin No.
Mnemonic
Type1
Description
11
NTRST
I
JTAG Test Reset. This reset input pin is one of the standard 5-pin JTAG debug ports on the part.
NTRST is an input pin only and has an internal, weak pull-down resistor. This pin remains
unconnected when not in use. NTRST is also monitored by the on-chip kernel to enable LIN
boot load mode.
12
TMS
I
JTAG Test Mode Select. This mode select input pin is one of the standard 5-pin JTAG debug ports
on the part. TMS is an input pin only and has an internal, weak pull-up resistor. This pin is left
unconnected when not in use.
13
VBAT
I
Battery Voltage Input to Resistor Divider.
14
VREF
I
External Reference Input Terminal. When this input is not used, connect it directly to the AGND
system ground. It can also be left unconnected.
15
GND_SW
I
Switch to Internal Analog Ground Reference. This pin is the negative input for the external
temperature channel and external reference. When this input is not used, connect it directly to
the AGND system ground.
18
VTEMP
I
External Pin for NTC/PTC Temperature Measurement.
19
IIN+
I
Positive Differential Input for Current Channel.
20
IIN
I
Negative Differential Input for Current Channel.
21, 22
AGND
S
Ground Reference for On-Chip Precision Analog Circuits.
24
REG_AVDD
S
Nominal 2.6 V Output from On-Chip Regulator.
27
GPIO_0/IRQ0/SS
I/O
General-Purpose Digital I/O 0/External Interrupt Request 0/Slave Select Input for SPI Interface.
By default and after power-on reset, this pin is configured as an input. The pin has an internal,
weak pull-up resistor and should be left unconnected when not in use.
28
GPIO_1/SCLK
I/O
General-Purpose Digital I/O 1/Serial Clock Input for SPI Interface. By default and after a power-
on reset, this pin is configured as an input. The pin has an internal, weak pull-up resistor and
should be left unconnected when not in use.
29
GPIO_2/MISO
I/O
General-Purpose Digital I/O 2/Master Input, Slave Output for SPI Interface. By default and after a
power-on reset, this pin is configured as an input. The pin has an internal, weak pull-up resistor
and should be left unconnected when not in use.
30
GPIO_3/MOSI
I/O
General-Purpose Digital I/O 3/Master Output, Slave Input for SPI Interface. By default and after a
power-on reset, this pin is configured as an input. The pin has an internal, weak pull-up resistor
and should be left unconnected when not in use.
31
GPIO_4/ECLK
I/O
General-Purpose Digital I/O 4/2.56 MHz Clock Output. By default and after a power-on reset, this
pin is configured as an input. The pin has an internal, weak pull-up resistor and should be left
unconnected when not in use.
33
REG_DVDD
S
Nominal 2.6 V Output from the On-Chip Regulator.
36
XTAL1
O
Crystal Oscillator Output. If an external crystal is not used, this pin is left unconnected.
37
XTAL2
I
Crystal Oscillator Input. If an external crystal is not used, connect this pin to the DGND system
ground.
41
WU
I/O
High Voltage Wake-Up Pin. This high voltage I/O pin has an internal, 10 kΩ pull-down resistor
and a high-side driver to VDD. If this pin is not being used, it should not be connected externally.
42
VDD
S
Battery Power Supply to On-Chip Regulator.
44
VSS
S
Ground Reference. This is the ground reference for the internal voltage regulators.
46
STI
I/O
High Voltage Serial Test Interface Output Pin. If this pin is not used, externally connect it to the
IO_VSS ground reference.
47
IO_VSS
S
Ground Reference for High Voltage I/O Pins.
48
LIN/BSD
I/O
Local Interconnect Network I/O/Bit Serial Device I/O. This is a high voltage pin.
EPAD
Exposed pad
The exposed pad should be connected to DGND.
1 I = input, O = output, I/O = input/output, S = supply.
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