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| 型號： | EVAL-ADUC7036QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 122/132頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7036 |
| 設計資源： | EVAL-ADUC7036 Schematic & Brd Outline EVAL ADUC7036 Gerber Files |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 主要目的： | 電源管理，電池監(jiān)控器 |
| 嵌入式： | 是，MCU，16/32 位 |
| 已用 IC / 零件： | ADuC7036 |
| 已供物品： | 板，線纜，文檔，仿真器，電源，軟件 |
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ADuC7036
Rev. C | Page 9 of 132
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
PACKAGE THERMAL SPECIFICATIONS
140
150
160
°C
48-lead LFCSP, stacked die
45
°C/W
POWER REQUIREMENTS
Power Supply Voltages
VDD (Battery Supply)
3.5
18
V
REG_DVDD, REG_AVDD33
2.5
2.6
2.7
V
Power Consumption
MCU clock rate = 10.24 MHz, ADC off
10
20
mA
MCU clock rate = 20.48 MHz, ADC off (valid for
ADuC7036CCPZ and ADuC7036DCPZ only)
20
30
mA
ADC low power mode, measured over the range of
TA = 10°C to +40°C, continuous ADC conversion
300
400
μA
ADC low power mode, measured over the range of
TA = 40°C to +85°C, continuous ADC conversion
300
500
μA
ADC low power plus mode, measured over the
range of TA = 10°C to +40°C, continuous ADC
conversion
520
700
μA
Average current, measured with wake-up and
watchdog timer clocked from the low power
oscillator, TA = 40°C to +85°C
120
300
μA
IDD (MCU Powered Down)
Average current, measured with wake-up and
watchdog timer clocked from low power oscillator
over a range of TA = 10°C to +40°C
120
175
μA
IDD (Current ADC)
1.7
mA
IDD (Voltage/Temperature ADC)
0.5
mA
IDD (Precision Oscillator)
400
μA
1 These numbers are not production tested but are guaranteed by design and/or characterization data at production release.
2 Valid for current ADC gain setting of PGA = 4 to 64.
3 These numbers include temperature drift.
4 Tested at gain range = 4; self-offset calibration removes this error.
5 Measured with an internal short after an initial offset calibration.
6 Measured with an internal short.
7 These numbers include internal reference temperature drift.
8 Factory-calibrated at gain = 1.
9 System calibration at a specific gain range (and temperature) removes the error at this gain range (and temperature).
10 Includes an initial system calibration.
11 Using ADC normal mode voltage reference.
12 Typical noise in low power modes is measured with chop enabled.
13 Voltage channel specifications include resistive attenuator input stage.
14 System calibration removes this error at the specified temperature.
15 RMS noise is referred to voltage attenuator input (for example, at fADC = 1 kHz, typical rms noise at the ADC input is 7.5 μV) and scaled by the attenuator (divide-by-24)
to yield these input referred noise specifications/values.
16 Valid after an initial self-calibration.
17 In ADC low power mode, the input range is fixed at ±9.375 mV. In ADC low power plus mode, the input range is fixed at ±2.34375 mV.
18 It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach
can also be used to reduce the ADC input range (LSB size).
19 Limited by minimum/maximum absolute input voltage range.
20 Valid for a differential input less than 10 mV.
21 Measured using box method.
22 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
23 References of up to REG_AVDD can be accommodated by enabling an internal divide-by-2.
24 Die temperature.
25 Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at 40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
26 Retention lifetime equivalent at junction temperature (TJ) of 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
27 Low power oscillator can be calibrated against either the precision oscillator or the external 32.768 kHz crystal in user code.
28 These numbers are not production tested, but are supported by LIN compliance testing.
29 BSD electrical specifications, except high and low voltage levels, are per LIN 2.0 with pull-up resistor disabled and CL = 10 nF maximum.
30 Specified after RLIMIT of 39 Ω.
31 The MCU core is not shut down but interrupted, and high voltage I/O pins are disabled in response to a thermal shutdown event.
32 Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature.
33 Internal regulated supply available at REG_DVDD (ISOURCE = 5 mA), and REG_AVDD (ISOURCE = 1 mA).
34 The specification listed is typical; additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.
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