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參數(shù)資料
| 型號(hào)： | EVAL-ADUC7036QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 127/132頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7036 |
| 設(shè)計(jì)資源： | EVAL-ADUC7036 Schematic & Brd Outline EVAL ADUC7036 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 主要目的： | 電源管理，電池監(jiān)控器 |
| 嵌入式： | 是，MCU，16/32 位 |
| 已用 IC / 零件： | ADuC7036 |
| 已供物品： | 板，線纜，文檔，仿真器，電源，軟件 |
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ADuC7036
Rev. C | Page 94 of 132
GPIO Port1 Clear Register
Name: GP1CLR
Address: 0xFFFF0D38
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish
this using the GP1CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP1DAT).
Table 69. GP1CLR MMR Bit Designations
Bit
Description
31 to 18
Reserved. These bits are reserved and should be written as 0 by user code.
17
Port 1.1 clear bit.
Set to 1 by user code to clear the external GPIO_6 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_6 pin.
16
Port 1.0 clear bit.
Set to 1 by user code to clear the external GPIO_5 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_5 pin.
15 to 0
Reserved. These bits are reserved and should be written as 0 by user code.
GPIO Port2 Clear Register
Name: GP2CLR
Address: 0xFFFF0D48
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish
this using the GP2CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP2DAT).
Table 70. GP2CLR MMR Bit Designations
Bit
Description
31 to 23
Reserved. These bits are reserved and should be written as 0 by user code.
22
Port 2.6 clear bit.
Set to 1 by user code to clear the external GPIO_13 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin.
21
Port 2.5 clear bit.
Set to 1 by user code to clear the external GPIO_12 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin.
20 to 18
Reserved. These bits are reserved and should be written as 0 by user code.
17
Port 2.1 clear bit.
Set to 1 by user code to clear the external GPIO_8 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin.
16
Port 2.0 clear bit.
Set to 1 by user code to clear the external GPIO_7 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin.
15 to 0
Reserved. These bits are reserved and should be written as 0 by user code.
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