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| 型號： | EVAL-ADUC7036QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/132頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7036 |
| 設(shè)計資源： | EVAL-ADUC7036 Schematic & Brd Outline EVAL ADUC7036 Gerber Files |
| 標(biāo)準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 主要目的： | 電源管理，電池監(jiān)控器 |
| 嵌入式： | 是，MCU，16/32 位 |
| 已用 IC / 零件： | ADuC7036 |
| 已供物品： | 板，線纜，文檔，仿真器，電源，軟件 |
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ADuC7036
Rev. C | Page 110 of 132
SERIAL PERIPHERAL INTERFACE
In master mode, polarity and phase of the clock is controlled by
the SPICON register, and the bit rate is defined in the SPIDIV
register using the SPI baud rate calculation, as follows:
The ADuC7036 features a complete hardware serial peripheral
interface (SPI) on chip. SPI is an industry-standard synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and received simultaneously, that is, full duplex.
)
1
(
2
MHz
48
.
20
SPIDIV
f
CLOCK
SERIAL
+
×
=
(3)
The SPI interface is operational only with core clock divider bits
(POWCON[2:0] = 0000 or 001).
The maximum speed of the SPI clock is dependent on the clock
divider bits and is summarized in Table 88.
The SPI port can be configured for master or slave operation
and consists of four pins that are multiplexed with four GPIOs.
The four SPI pins are MISO, MOSI, SCLK, and SS. The pins to
which these signals are connected are shown in
.
Table 88. SPI Speed vs. Clock Divider Bits in Master Mode
Setting of CD Bits
SPIDIV
Maximum SCLK (MHz)
0
0x05
1.667
Table 87. SPI Output Pins
Pin
SPI
Pin Function
1
0x0B
0.833
Description
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data of up to 5.12 Mb from an external master when
CD = 0. The formula to determine the maximum speed is as
follows:
GP0 (GPIO Mode 1)
SS
Chip select
GP1 (GPIO Mode 1)
SCLK
Serial clock
GP2 (GPIO Mode 1)
MISO
Master input, slave output
GP3 (GPIO Mode 1)
MOSI
Master output, slave input
4
HCLK
CLOCK
SERIAL
f
=
(4)
MISO PIN
The MISO (master input, slave output) pin is configured as an
input line in master mode and as an output line in slave mode.
The MISO line on the master (data in) should be connected to
the MISO line in the slave device (data out). The data is transferred
as byte-wide (8-bit) serial data, MSB first.
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important to use the same polarity and phase configurations for
the master and slave devices.
SS PIN
MOSI PIN
The MOSI (master output, slave input) pin is configured as an
output line in master mode and as an input line in slave mode.
The MOSI line on the master (data out) should be connected to
the MOSI line in the slave device (data in). The data is transferred
as byte-wide (8-bit) serial data, MSB first.
In SPI slave mode, a transfer is initiated by the assertion of SS,
an active low input signal. The SPI port transmits and receives
eight bits of data, and then the transfer is concluded by the
deassertion of SS. In slave mode, SS is always an input.
SPI REGISTER DEFINITIONS
SCLK PIN
The following MMR registers are used to control the SPI
interface:
The SCLK (master serial clock) pin is used to synchronize the
data being transmitted and received through the MOSI SCLK
period. Therefore, a byte is transmitted/received after eight
SCLK periods. The SCLK pin is configured as an output in
master mode and as an input in slave mode.
SPICON: 16-bit control register
SPISTA: 8-bit, read only status register
SPIDIV: 8-bit, serial clock divider register
SPITX: 8-bit, write only transmit register
SPIRX: 8-bit, read only receive register
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