參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 30/132頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7036
設(shè)計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 125 of 132
BSD RELATED MMRS
The ADuC7036 emulates the BSD communication protocol
using a software (bit bang) interface with some hardware assis-
tance form LIN hardware synchronization logic. In effect, the
ADuC7036 BSD interface uses the following protocols:
An internal GPIO signal (GPIO_12) that is routed to the
external LIN/BSD pin and is controlled directly by software
to generate 0s and 1s.
When reading bits, the LIN synchronization hardware uses
LHSVAL1 to count the width of the incoming pulses so
that user code can interpret the bits as sync, 0, or 1.
When writing bits, user code toggles a GPIO pin and uses
the LHSCAP and LHSCMP registers to time pulse widths
and generate an interrupt when the BSD output pulse width
has reached its required width.
The ADuC7036 MMRs required for BSD communication are as
follows:
LHSSTA: LIN hardware synchronization status register
LHSCON0: LIN hardware synchronization control register
LHSVAL0: LIN hardware synchronization Timer0
(16-bit timer)
LHSCON1: LIN hardware synchronization edge setup
register
LHSVAL1: LIN hardware synchronization break timer
LHSCAP: LIN hardware synchronization capture register
LHSCMP: LIN hardware synchronization compare register
IRQEN/IRQCLR: enable interrupt register
FIQEN/FIQCLR: enable fast interrupt register
GP2DAT: GPIO Port 2 data register
GP2SET: GPIO Port 2 set register
GP2CLR: GPIO Port 2 clear register
Detailed bit definitions for most of these MMRs have been
listed previously. In addition to the registers described in the
LIN MMR Description section, LHSCAP and LHSCMP are
registers that are required for the operation of the BSD
interface. Details of these registers follow.
LIN Hardware Synchronization Capture Register
Name: LHSCAP
Address: 0xFFFF0794
Default Value: 0x0000
Access: Read only
Function: This 16-bit, read only register holds the last captured
value of the internal LIN synchronization timer (LHSVAL0). In
BSD mode, LHSVAL0 is clocked directly from an internal
5 MHz clock, and its value is loaded into the capture register on
every falling edge of the BSD bus.
LIN Hardware Synchronization Compare Register
Name: LHSCMP
Address: 0xFFFF0798
Default Value: 0x0000
Access: Read/write
Function: This register is used to time BSD output pulse widths.
When enabled through LHSCON0[5], a LIN interrupt is generated
when the value in LHSCAP equals the value written in LHSCMP.
This functionality allows user code to determine how long a BSD
transmission bit (sync, 0, or 1) should be asserted on the bus.
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